TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for the Freescale MCF5208EVBe. |
| 3 | * |
| 4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _M5208EVBE_H |
| 11 | #define _M5208EVBE_H |
| 12 | |
| 13 | /* |
| 14 | * High Level Configuration Options |
| 15 | * (easy to change) |
| 16 | */ |
| 17 | #define CONFIG_MCF520x /* define processor family */ |
| 18 | #define CONFIG_M5208 /* define processor type */ |
| 19 | |
| 20 | #define CONFIG_MCFUART |
| 21 | #define CONFIG_SYS_UART_PORT (0) |
| 22 | #define CONFIG_BAUDRATE 115200 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 23 | |
| 24 | #undef CONFIG_WATCHDOG |
| 25 | #define CONFIG_WATCHDOG_TIMEOUT 5000 |
| 26 | |
| 27 | /* Command line configuration */ |
| 28 | #include <config_cmd_default.h> |
| 29 | |
| 30 | #define CONFIG_CMD_CACHE |
| 31 | #define CONFIG_CMD_ELF |
| 32 | #define CONFIG_CMD_FLASH |
| 33 | #undef CONFIG_CMD_I2C |
| 34 | #define CONFIG_CMD_MEMORY |
| 35 | #define CONFIG_CMD_MISC |
| 36 | #define CONFIG_CMD_MII |
| 37 | #define CONFIG_CMD_NET |
| 38 | #define CONFIG_CMD_PING |
| 39 | #define CONFIG_CMD_REGINFO |
| 40 | |
| 41 | #define CONFIG_MCFFEC |
| 42 | #ifdef CONFIG_MCFFEC |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 43 | # define CONFIG_MII 1 |
| 44 | # define CONFIG_MII_INIT 1 |
| 45 | # define CONFIG_SYS_DISCOVER_PHY |
| 46 | # define CONFIG_SYS_RX_ETH_BUFFER 8 |
| 47 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 48 | # define CONFIG_HAS_ETH1 |
| 49 | |
| 50 | # define CONFIG_SYS_FEC0_PINMUX 0 |
| 51 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE |
| 52 | # define MCFFEC_TOUT_LOOP 50000 |
| 53 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 54 | # ifndef CONFIG_SYS_DISCOVER_PHY |
| 55 | # define FECDUPLEX FULL |
| 56 | # define FECSPEED _100BASET |
| 57 | # else |
| 58 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 59 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 60 | # endif |
| 61 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
| 62 | #endif |
| 63 | |
| 64 | /* Timer */ |
| 65 | #define CONFIG_MCFTMR |
| 66 | #undef CONFIG_MCFPIT |
| 67 | |
| 68 | /* I2C */ |
| 69 | #define CONFIG_FSL_I2C |
| 70 | #define CONFIG_HARD_I2C /* I2C with hw support */ |
| 71 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 72 | #define CONFIG_SYS_I2C_SPEED 80000 |
| 73 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 74 | #define CONFIG_SYS_I2C_OFFSET 0x58000 |
| 75 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
| 76 | |
| 77 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
| 78 | #define CONFIG_UDP_CHECKSUM |
| 79 | |
| 80 | #ifdef CONFIG_MCFFEC |
| 81 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
| 82 | # define CONFIG_IPADDR 192.162.1.2 |
| 83 | # define CONFIG_NETMASK 255.255.255.0 |
| 84 | # define CONFIG_SERVERIP 192.162.1.1 |
| 85 | # define CONFIG_GATEWAYIP 192.162.1.1 |
| 86 | # define CONFIG_OVERWRITE_ETHADDR_ONCE |
| 87 | #endif /* CONFIG_MCFFEC */ |
| 88 | |
| 89 | #define CONFIG_HOSTNAME M5208EVBe |
| 90 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 91 | "netdev=eth0\0" \ |
| 92 | "loadaddr=40010000\0" \ |
| 93 | "u-boot=u-boot.bin\0" \ |
| 94 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 95 | "upd=run load; run prog\0" \ |
| 96 | "prog=prot off 0 3ffff;" \ |
| 97 | "era 0 3ffff;" \ |
| 98 | "cp.b ${loadaddr} 0 ${filesize};" \ |
| 99 | "save\0" \ |
| 100 | "" |
| 101 | |
| 102 | #define CONFIG_PRAM 512 /* 512 KB */ |
| 103 | #define CONFIG_SYS_PROMPT "-> " |
| 104 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 105 | |
| 106 | #ifdef CONFIG_CMD_KGDB |
| 107 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 108 | #else |
| 109 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 110 | #endif |
| 111 | |
| 112 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 113 | #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ |
| 114 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ |
| 115 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 |
| 116 | |
| 117 | #define CONFIG_SYS_HZ 1000 |
| 118 | #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ |
| 119 | #define CONFIG_SYS_PLL_ODR 0x36 |
| 120 | #define CONFIG_SYS_PLL_FDR 0x7D |
| 121 | |
| 122 | #define CONFIG_SYS_MBAR 0xFC000000 |
| 123 | |
| 124 | /* |
| 125 | * Low Level Configuration Settings |
| 126 | * (address mappings, register initial values, etc.) |
| 127 | * You should know what you are doing if you make changes here. |
| 128 | */ |
| 129 | /* Definitions for initial stack pointer and data area (in DPRAM) */ |
| 130 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 132 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 134 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 135 | |
| 136 | /* |
| 137 | * Start addresses for the final memory configuration |
| 138 | * (Set up by the startup code) |
| 139 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 140 | */ |
| 141 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
TsiChung Liew | f6f4ec9 | 2010-03-10 18:50:22 -0600 | [diff] [blame] | 142 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 143 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 |
| 144 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 |
| 145 | #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 |
| 146 | #define CONFIG_SYS_SDRAM_EMOD 0x80010000 |
| 147 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 |
| 148 | |
| 149 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
| 150 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) |
| 151 | |
| 152 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| 153 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 154 | |
| 155 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
| 156 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 157 | |
| 158 | /* |
| 159 | * For booting Linux, the board info and command line data |
| 160 | * have to be in the first 8 MB of memory, since this is |
| 161 | * the maximum mapped by the Linux kernel during initialization ?? |
| 162 | */ |
| 163 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
| 164 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
| 165 | |
| 166 | /* FLASH organization */ |
| 167 | #define CONFIG_SYS_FLASH_CFI |
| 168 | #ifdef CONFIG_SYS_FLASH_CFI |
| 169 | # define CONFIG_FLASH_CFI_DRIVER 1 |
| 170 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
| 171 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 172 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 173 | # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ |
| 174 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
| 175 | #endif |
| 176 | |
| 177 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
| 178 | |
| 179 | /* |
| 180 | * Configuration for environment |
| 181 | * Environment is embedded in u-boot in the second sector of the flash |
| 182 | */ |
| 183 | #define CONFIG_ENV_OFFSET 0x2000 |
| 184 | #define CONFIG_ENV_SIZE 0x1000 |
| 185 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
| 186 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 187 | |
| 188 | /* Cache Configuration */ |
| 189 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
| 190 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 191 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 192 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 193 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 194 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 195 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
| 196 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ |
| 197 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 198 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 199 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ |
| 200 | CF_CACR_DISD | CF_CACR_INVI | \ |
| 201 | CF_CACR_CEIB | CF_CACR_DCM | \ |
| 202 | CF_CACR_EUSP) |
| 203 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 204 | /* Chipselect bank definitions */ |
| 205 | /* |
| 206 | * CS0 - NOR Flash |
| 207 | * CS1 - Available |
| 208 | * CS2 - Available |
| 209 | * CS3 - Available |
| 210 | * CS4 - Available |
| 211 | * CS5 - Available |
| 212 | */ |
| 213 | #define CONFIG_SYS_CS0_BASE 0 |
| 214 | #define CONFIG_SYS_CS0_MASK 0x007F0001 |
| 215 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 |
| 216 | |
| 217 | #endif /* _M5208EVBE_H */ |