blob: dd74bb9e08719812262a7d036db375f12d95c4aa [file] [log] [blame]
Jim Liu4359b332022-04-19 13:32:19 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2021 Nuvoton Technology Corp.
4 */
5
6#include <common.h>
7#include <cpu_func.h>
8#include <asm/armv7.h>
9#include <asm/io.h>
10#include <asm/arch/gcr.h>
11
12int print_cpuinfo(void)
13{
14 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
15 unsigned int id, mdlr;
16
17 mdlr = readl(&gcr->mdlr);
18
19 printf("CPU: ");
20
21 switch (mdlr) {
22 case POLEG_NPCM750:
23 printf("NPCM750 ");
24 break;
25 case POLEG_NPCM730:
26 printf("NPCM730 ");
27 break;
28 case POLEG_NPCM710:
29 printf("NPCM710 ");
30 break;
31 default:
32 printf("NPCM7XX ");
33 break;
34 }
35
36 id = readl(&gcr->pdid);
37 switch (id) {
38 case POLEG_Z1:
39 printf("Z1 is no supported! @ ");
40 break;
41 case POLEG_A1:
42 printf("A1 @ ");
43 break;
44 default:
45 printf("Unknown\n");
46 break;
47 }
48
49 return 0;
50}
51
52void s_init(void)
53{
54 /* Invalidate L2 cache in lowlevel_init */
55 v7_outer_cache_inval_all();
56}
57
58void enable_caches(void)
59{
60 dcache_enable();
61}
62
63void disable_caches(void)
64{
65 dcache_disable();
66}