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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wu, Josh3f338c12013-04-16 23:42:44 +00002/*
3 * (C) Copyright 2013 Atmel Corporation.
4 * Josh Wu <josh.wu@atmel.com>
5 *
6 * Configuation settings for the AT91SAM9N12-EK boards.
Wu, Josh3f338c12013-04-16 23:42:44 +00007 */
8
9#ifndef __AT91SAM9N12_CONFIG_H_
10#define __AT91SAM9N12_CONFIG_H_
11
Wu, Josh3f338c12013-04-16 23:42:44 +000012/* ARM asynchronous clock */
13#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
14#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
Wu, Josh3f338c12013-04-16 23:42:44 +000015
16/* Misc CPU related */
Wu, Josh3f338c12013-04-16 23:42:44 +000017#define CONFIG_SYS_SDRAM_BASE 0x20000000
18#define CONFIG_SYS_SDRAM_SIZE 0x08000000
19
Wu, Josh3f338c12013-04-16 23:42:44 +000020/* DataFlash */
Wu, Josh3f338c12013-04-16 23:42:44 +000021
22/* NAND flash */
23#ifdef CONFIG_CMD_NAND
Wu, Josh3f338c12013-04-16 23:42:44 +000024#define CONFIG_SYS_NAND_BASE 0x40000000
25#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
26#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmanna4c24d32013-11-29 12:13:45 +010027#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
28#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
Tom Rini00448d22017-07-28 21:31:42 -040029#endif
Wu, Josh3f338c12013-04-16 23:42:44 +000030
Wu, Josh3f338c12013-04-16 23:42:44 +000031#define CONFIG_EXTRA_ENV_SETTINGS \
32 "console=console=ttyS0,115200\0" \
Wu, Josh3f338c12013-04-16 23:42:44 +000033 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
34 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
35
Bo Shen9c709392015-03-27 14:23:36 +080036/* SPL */
Bo Shen9c709392015-03-27 14:23:36 +080037
Bo Shen9c709392015-03-27 14:23:36 +080038#define CONFIG_SYS_MASTER_CLOCK 132096000
39#define CONFIG_SYS_AT91_PLLA 0x20953f03
40#define CONFIG_SYS_MCKR 0x1301
41#define CONFIG_SYS_MCKR_CSS 0x1302
42
Wu, Josh3f338c12013-04-16 23:42:44 +000043#endif