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git01.mediatek.com / filogic / uboot / fb782f58f4fd0fb1b1ff6999c894c20e4053ddc0 / . / include / fsl_dspi.h
blob: ebe1803e4665440c8a0a337df8c9e543f68551ec [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Haikun.Wang@freescale.coma28e2912015-03-24 22:03:58 +0800[diff] [blame]2/*
3 * Freescale DSPI Module Defines
4 *
5 * Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * Chao Fu (B44548@freesacle.com)
8 * Haikun Wang (B53464@freescale.com)
Haikun.Wang@freescale.coma28e2912015-03-24 22:03:58 +0800[diff] [blame]9 */
10
11#ifndef _FSL_DSPI_H_
12#define _FSL_DSPI_H_
13
14/* DMA Serial Peripheral Interface (DSPI) */
15struct dspi {
16 u32 mcr; /* 0x00 */
17 u32 resv0; /* 0x04 */
18 u32 tcr; /* 0x08 */
19 u32 ctar[8]; /* 0x0C - 0x28 */
20 u32 sr; /* 0x2C */
21 u32 irsr; /* 0x30 */
22 u32 tfr; /* 0x34 - PUSHR */
23 u32 rfr; /* 0x38 - POPR */
Haikun.Wang@freescale.coma28e2912015-03-24 22:03:58 +0800[diff] [blame]24 u32 tfdr[16]; /* 0x3C */
25 u32 rfdr[16]; /* 0x7C */
Haikun.Wang@freescale.coma28e2912015-03-24 22:03:58 +0800[diff] [blame]26};
27
28/* Module configuration */
29#define DSPI_MCR_MSTR 0x80000000
30#define DSPI_MCR_CSCK 0x40000000
31#define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28)
32#define DSPI_MCR_FRZ 0x08000000
33#define DSPI_MCR_MTFE 0x04000000
34#define DSPI_MCR_PCSSE 0x02000000
35#define DSPI_MCR_ROOE 0x01000000
36#define DSPI_MCR_PCSIS(x) (1 << (16 + (x)))
37#define DSPI_MCR_PCSIS_MASK (0xff << 16)
38#define DSPI_MCR_CSIS7 0x00800000
39#define DSPI_MCR_CSIS6 0x00400000
40#define DSPI_MCR_CSIS5 0x00200000
41#define DSPI_MCR_CSIS4 0x00100000
42#define DSPI_MCR_CSIS3 0x00080000
43#define DSPI_MCR_CSIS2 0x00040000
44#define DSPI_MCR_CSIS1 0x00020000
45#define DSPI_MCR_CSIS0 0x00010000
46#define DSPI_MCR_DOZE 0x00008000
47#define DSPI_MCR_MDIS 0x00004000
48#define DSPI_MCR_DTXF 0x00002000
49#define DSPI_MCR_DRXF 0x00001000
50#define DSPI_MCR_CTXF 0x00000800
51#define DSPI_MCR_CRXF 0x00000400
52#define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8)
53#define DSPI_MCR_FCPCS 0x00000001
54#define DSPI_MCR_PES 0x00000001
55#define DSPI_MCR_HALT 0x00000001
56
57/* Transfer count */
58#define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16)
59
60/* Clock and transfer attributes */
61#define DSPI_CTAR(x) (0x0c + (x * 4))
62#define DSPI_CTAR_DBR 0x80000000
63#define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27)
64#define DSPI_CTAR_CPOL 0x04000000
65#define DSPI_CTAR_CPHA 0x02000000
66#define DSPI_CTAR_LSBFE 0x01000000
67#define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22)
68#define DSPI_CTAR_PCSSCK_7CLK 0x00A00000
69#define DSPI_CTAR_PCSSCK_5CLK 0x00800000
70#define DSPI_CTAR_PCSSCK_3CLK 0x00400000
71#define DSPI_CTAR_PCSSCK_1CLK 0x00000000
72#define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20)
73#define DSPI_CTAR_PASC_7CLK 0x00300000
74#define DSPI_CTAR_PASC_5CLK 0x00200000
75#define DSPI_CTAR_PASC_3CLK 0x00100000
76#define DSPI_CTAR_PASC_1CLK 0x00000000
77#define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18)
78#define DSPI_CTAR_PDT_7CLK 0x000A0000
79#define DSPI_CTAR_PDT_5CLK 0x00080000
80#define DSPI_CTAR_PDT_3CLK 0x00040000
81#define DSPI_CTAR_PDT_1CLK 0x00000000
82#define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16)
83#define DSPI_CTAR_PBR_7CLK 0x00030000
84#define DSPI_CTAR_PBR_5CLK 0x00020000
85#define DSPI_CTAR_PBR_3CLK 0x00010000
86#define DSPI_CTAR_PBR_1CLK 0x00000000
87#define DSPI_CTAR_CSSCK(x) (((x) & 0x0F) << 12)
88#define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8)
89#define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4)
90#define DSPI_CTAR_BR(x) ((x) & 0x0F)
Vladimir Oltean2926f572020-05-04 11:24:26 +0300[diff] [blame]91#define DSPI_CTAR_SCALE_BITS 0xf
Haikun.Wang@freescale.coma28e2912015-03-24 22:03:58 +0800[diff] [blame]92
93/* Status */
94#define DSPI_SR_TCF 0x80000000
95#define DSPI_SR_TXRXS 0x40000000
96#define DSPI_SR_EOQF 0x10000000
97#define DSPI_SR_TFUF 0x08000000
98#define DSPI_SR_TFFF 0x02000000
99#define DSPI_SR_RFOF 0x00080000
100#define DSPI_SR_RFDF 0x00020000
101#define DSPI_SR_TXCTR(x) (((x) & 0x0000F000) >> 12)
102#define DSPI_SR_TXPTR(x) (((x) & 0x00000F00) >> 8)
103#define DSPI_SR_RXCTR(x) (((x) & 0x000000F0) >> 4)
104#define DSPI_SR_RXPTR(x) ((x) & 0x0000000F)
105
106/* DMA/interrupt request selct and enable */
107#define DSPI_IRSR_TCFE 0x80000000
108#define DSPI_IRSR_EOQFE 0x10000000
109#define DSPI_IRSR_TFUFE 0x08000000
110#define DSPI_IRSR_TFFFE 0x02000000
111#define DSPI_IRSR_TFFFS 0x01000000
112#define DSPI_IRSR_RFOFE 0x00080000
113#define DSPI_IRSR_RFDFE 0x00020000
114#define DSPI_IRSR_RFDFS 0x00010000
115
116/* Transfer control - 32-bit access */
117#define DSPI_TFR_PCS(x) (((1 << x) & 0x0000003f) << 16)
118#define DSPI_TFR_CONT 0x80000000
119#define DSPI_TFR_CTAS(x) (((x) & 0x07) << 28)
120#define DSPI_TFR_EOQ 0x08000000
121#define DSPI_TFR_CTCNT 0x04000000
122#define DSPI_TFR_CS7 0x00800000
123#define DSPI_TFR_CS6 0x00400000
124#define DSPI_TFR_CS5 0x00200000
125#define DSPI_TFR_CS4 0x00100000
126#define DSPI_TFR_CS3 0x00080000
127#define DSPI_TFR_CS2 0x00040000
128#define DSPI_TFR_CS1 0x00020000
129#define DSPI_TFR_CS0 0x00010000
130
131/* Transfer Fifo */
132#define DSPI_TFR_TXDATA(x) ((x) & 0x0000FFFF)
133
134/* Bit definitions and macros for DRFR */
135#define DSPI_RFR_RXDATA(x) ((x) & 0x0000FFFF)
136
137/* Bit definitions and macros for DTFDR group */
138#define DSPI_TFDR_TXDATA(x) ((x) & 0x0000FFFF)
139#define DSPI_TFDR_TXCMD(x) (((x) & 0x0000FFFF) << 16)
140
141/* Bit definitions and macros for DRFDR group */
142#define DSPI_RFDR_RXDATA(x) ((x) & 0x0000FFFF)
143
144#endif /* _FSL_DSPI_H_ */