| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
| Patrice Chotard | 5d9950d | 2020-12-02 18:47:30 +0100 | [diff] [blame] | 4 | * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. |
| Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __STM32_PWR_H_ |
| Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 8 | #define __STM32_PWR_H_ |
| 9 | |
| 10 | #ifndef __ASSEMBLY__ |
| 11 | #include <linux/bitops.h> |
| 12 | #endif |
| Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 13 | |
| 14 | /* |
| 15 | * Offsets of some PWR registers |
| 16 | */ |
| 17 | #define PWR_CR1_ODEN BIT(16) |
| 18 | #define PWR_CR1_ODSWEN BIT(17) |
| 19 | #define PWR_CSR1_ODRDY BIT(16) |
| 20 | #define PWR_CSR1_ODSWRDY BIT(17) |
| 21 | |
| 22 | struct stm32_pwr_regs { |
| 23 | u32 cr1; /* power control register 1 */ |
| 24 | u32 csr1; /* power control/status register 2 */ |
| 25 | }; |
| 26 | |
| 27 | #endif /* __STM32_PWR_H_ */ |