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Peng Fanca09d4c2019-04-22 10:41:28 +00001menu "i.MX8M DDR controllers"
2 depends on ARCH_IMX8M
3
Peng Fan692f9432018-11-20 10:19:57 +00004config IMX8M_DRAM
5 bool "imx8m dram"
6
7config IMX8M_LPDDR4
8 bool "imx8m lpddr4"
9 select IMX8M_DRAM
10 help
11 Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
12
13config IMX8M_DDR4
14 bool "imx8m ddr4"
15 select IMX8M_DRAM
16 help
17 Select the i.MX8M DDR4 driver support on i.MX8M SOC.
18
Jacky Baid62ddc12019-08-08 09:59:08 +000019config IMX8M_DDR3L
20 bool "imx8m ddr3l"
21 select IMX8M_DRAM
22 help
23 Select the i.MX8M DDR3L driver support on i.MX8M SOC.
24
Peng Fan692f9432018-11-20 10:19:57 +000025config SAVED_DRAM_TIMING_BASE
26 hex "Define the base address for saved dram timing"
27 help
28 after DRAM is trained, need to save the dram related timming
29 info into memory for low power use. OCRAM_S is used for this
30 purpose on i.MX8MM.
31 default 0x180000
Peng Fanca09d4c2019-04-22 10:41:28 +000032endmenu