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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +02002/*
3 * Qualcomm UART driver
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * UART will work in Data Mover mode.
8 * Based on Linux driver.
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +02009 */
10
11#include <common.h>
12#include <clk.h>
13#include <dm.h>
14#include <errno.h>
Simon Glass9bc15642020-02-03 07:36:16 -070015#include <malloc.h>
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +020016#include <serial.h>
17#include <watchdog.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060018#include <asm/global_data.h>
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +020019#include <asm/io.h>
20#include <linux/compiler.h>
Stephan Gerhold9a4569f2021-07-14 10:56:26 +020021#include <linux/delay.h>
Ramon Fried2292ed32018-05-16 12:13:42 +030022#include <dm/pinctrl.h>
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +020023
24/* Serial registers - this driver works in uartdm mode*/
25
26#define UARTDM_DMRX 0x34 /* Max RX transfer length */
Stephan Gerhold706d4812021-06-28 10:40:09 +020027#define UARTDM_DMEN 0x3C /* DMA/data-packing mode */
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +020028#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
29
30#define UARTDM_RXFS 0x50 /* RX channel status register */
31#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
32#define UARTDM_RXFS_BUF_MASK 0x7
Ramon Fried2292ed32018-05-16 12:13:42 +030033#define UARTDM_MR1 0x00
34#define UARTDM_MR2 0x04
Caleb Connollyfb47e062024-04-15 16:03:40 +010035/*
36 * This is documented on page 1817 of the apq8016e technical reference manual.
37 * section 6.2.5.3.26
38 *
39 * The upper nybble contains the bit clock divider for the RX pin, the lower
40 * nybble defines the TX pin. In almost all cases these should be the same value.
41 *
42 * The baud rate is the core clock frequency divided by the fixed divider value
43 * programmed into this register (defined in calc_csr_bitrate()).
44 */
Ramon Fried2292ed32018-05-16 12:13:42 +030045#define UARTDM_CSR 0xA0
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +020046
47#define UARTDM_SR 0xA4 /* Status register */
48#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
49#define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
50#define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
51
52#define UARTDM_CR 0xA8 /* Command register */
53#define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
54#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
55#define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
56#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
57#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
58
59#define UARTDM_IMR 0xB0 /* Interrupt mask register */
60#define UARTDM_ISR 0xB4 /* Interrupt status register */
61#define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
62
63#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
64#define UARTDM_RF 0x140 /* UART Receive FIFO register */
65
Ramon Fried2292ed32018-05-16 12:13:42 +030066#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
67#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
68#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +020069
70DECLARE_GLOBAL_DATA_PTR;
71
72struct msm_serial_data {
73 phys_addr_t base;
74 unsigned chars_cnt; /* number of buffered chars */
75 uint32_t chars_buf; /* buffered chars */
Caleb Connollyfb47e062024-04-15 16:03:40 +010076 uint32_t clk_rate; /* core clock rate */
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +020077};
78
79static int msm_serial_fetch(struct udevice *dev)
80{
81 struct msm_serial_data *priv = dev_get_priv(dev);
82 unsigned sr;
83
84 if (priv->chars_cnt)
85 return priv->chars_cnt;
86
87 /* Clear error in case of buffer overrun */
88 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
89 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
90
91 /* We need to fetch new character */
92 sr = readl(priv->base + UARTDM_SR);
93
94 if (sr & UARTDM_SR_RX_READY) {
95 /* There are at least 4 bytes in fifo */
96 priv->chars_buf = readl(priv->base + UARTDM_RF);
97 priv->chars_cnt = 4;
98 } else {
99 /* Check if there is anything in fifo */
100 priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
101 /* Extract number of characters in UART packing buffer*/
102 priv->chars_cnt = (priv->chars_cnt >>
103 UARTDM_RXFS_BUF_SHIFT) &
104 UARTDM_RXFS_BUF_MASK;
105 if (!priv->chars_cnt)
106 return 0;
107
108 /* There is at least one charcter, move it to fifo */
109 writel(UARTDM_CR_CMD_FORCE_STALE,
110 priv->base + UARTDM_CR);
111
112 priv->chars_buf = readl(priv->base + UARTDM_RF);
113 writel(UARTDM_CR_CMD_RESET_STALE_INT,
114 priv->base + UARTDM_CR);
115 writel(0x7, priv->base + UARTDM_DMRX);
116 }
117
118 return priv->chars_cnt;
119}
120
121static int msm_serial_getc(struct udevice *dev)
122{
123 struct msm_serial_data *priv = dev_get_priv(dev);
124 char c;
125
126 if (!msm_serial_fetch(dev))
127 return -EAGAIN;
128
129 c = priv->chars_buf & 0xFF;
130 priv->chars_buf >>= 8;
131 priv->chars_cnt--;
132
133 return c;
134}
135
136static int msm_serial_putc(struct udevice *dev, const char ch)
137{
138 struct msm_serial_data *priv = dev_get_priv(dev);
139
140 if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
141 !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
142 return -EAGAIN;
143
144 writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
145
146 writel(1, priv->base + UARTDM_NCF_TX);
147 writel(ch, priv->base + UARTDM_TF);
148
149 return 0;
150}
151
152static int msm_serial_pending(struct udevice *dev, bool input)
153{
154 if (input) {
155 if (msm_serial_fetch(dev))
156 return 1;
157 }
158
159 return 0;
160}
161
162static const struct dm_serial_ops msm_serial_ops = {
163 .putc = msm_serial_putc,
164 .pending = msm_serial_pending,
165 .getc = msm_serial_getc,
166};
167
Caleb Connollyfb47e062024-04-15 16:03:40 +0100168static long msm_uart_clk_init(struct udevice *dev)
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200169{
Caleb Connollyfb47e062024-04-15 16:03:40 +0100170 struct msm_serial_data *priv = dev_get_priv(dev);
Stephen Warrena9622432016-06-17 09:44:00 -0600171 struct clk clk;
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200172 int ret;
Caleb Connollyfb47e062024-04-15 16:03:40 +0100173 long rate;
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200174
Caleb Connolly7a9c7b92024-02-26 17:26:12 +0000175 ret = clk_get_by_name(dev, "core", &clk);
176 if (ret < 0) {
177 pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
Caleb Connollyfb47e062024-04-15 16:03:40 +0100178 return 0;
Caleb Connolly7a9c7b92024-02-26 17:26:12 +0000179 }
Stephen Warrena9622432016-06-17 09:44:00 -0600180
Caleb Connollyfb47e062024-04-15 16:03:40 +0100181 rate = clk_set_rate(&clk, priv->clk_rate);
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200182
Caleb Connollyfb47e062024-04-15 16:03:40 +0100183 return rate;
184}
185
186static int calc_csr_bitrate(struct msm_serial_data *priv)
187{
188 /* This table is from the TRE. See the definition of UARTDM_CSR */
189 unsigned int csr_div_table[] = {24576, 12288, 6144, 3072, 1536, 768, 512, 384,
190 256, 192, 128, 96, 64, 48, 32, 16};
191 int i = ARRAY_SIZE(csr_div_table) - 1;
192 /* Currently we only support one baudrate */
193 int baud = 115200;
194
195 for (; i >= 0; i--) {
196 int x = priv->clk_rate / csr_div_table[i];
197
198 if (x == baud)
199 /* Duplicate the configuration for RX
200 * as the lower nybble only configures TX
201 */
202 return i + (i << 4);
203 }
204
205 return -EINVAL;
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200206}
207
Ramon Fried2292ed32018-05-16 12:13:42 +0300208static void uart_dm_init(struct msm_serial_data *priv)
209{
Stephan Gerhold9a4569f2021-07-14 10:56:26 +0200210 /* Delay initialization for a bit to let pins stabilize if necessary */
211 mdelay(5);
Caleb Connollyfb47e062024-04-15 16:03:40 +0100212 int bitrate = calc_csr_bitrate(priv);
213 if (bitrate < 0) {
214 log_warning("Couldn't calculate bit clock divider! Using default\n");
215 /* This happens to be the value used on MSM8916 for the hardcoded clockrate
216 * in clock-apq8016. It's at least a better guess than a value we *know*
217 * is wrong...
218 */
219 bitrate = 0xCC;
220 }
Stephan Gerhold9a4569f2021-07-14 10:56:26 +0200221
Caleb Connollyfb47e062024-04-15 16:03:40 +0100222 writel(bitrate, priv->base + UARTDM_CSR);
Ramon Fried2292ed32018-05-16 12:13:42 +0300223 writel(0x0, priv->base + UARTDM_MR1);
224 writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
225 writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
226 writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
Stephan Gerhold706d4812021-06-28 10:40:09 +0200227
228 /* Make sure BAM/single character mode is disabled */
229 writel(0x0, priv->base + UARTDM_DMEN);
Ramon Fried2292ed32018-05-16 12:13:42 +0300230}
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200231static int msm_serial_probe(struct udevice *dev)
232{
233 struct msm_serial_data *priv = dev_get_priv(dev);
Caleb Connollyfb47e062024-04-15 16:03:40 +0100234 long rate;
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200235
Ramon Fried1f0f4a12018-05-16 12:13:38 +0300236 /* No need to reinitialize the UART after relocation */
237 if (gd->flags & GD_FLG_RELOC)
238 return 0;
239
Caleb Connollyfb47e062024-04-15 16:03:40 +0100240 rate = msm_uart_clk_init(dev);
241 if (rate < 0)
242 return rate;
243 if (!rate) {
244 log_err("Got core clock rate of 0... Please fix your clock driver\n");
245 return -EINVAL;
246 }
247
248 /* Update the clock rate to the actual programmed rate returned by the
249 * clock driver
250 */
251 priv->clk_rate = rate;
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200252
Ramon Fried2292ed32018-05-16 12:13:42 +0300253 uart_dm_init(priv);
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200254
255 return 0;
256}
257
Simon Glassaad29ae2020-12-03 16:55:21 -0700258static int msm_serial_of_to_plat(struct udevice *dev)
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200259{
260 struct msm_serial_data *priv = dev_get_priv(dev);
Caleb Connollyfb47e062024-04-15 16:03:40 +0100261 int ret;
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200262
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900263 priv->base = dev_read_addr(dev);
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200264 if (priv->base == FDT_ADDR_T_NONE)
265 return -EINVAL;
266
Caleb Connollyfb47e062024-04-15 16:03:40 +0100267 ret = dev_read_u32(dev, "clock-frequency", &priv->clk_rate);
268 if (ret < 0) {
269 log_debug("No clock frequency specified, using default rate\n");
270 /* Default for APQ8016 */
271 priv->clk_rate = 7372800;
272 }
Robert Marko03a36022020-07-06 10:37:55 +0200273
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200274 return 0;
275}
276
277static const struct udevice_id msm_serial_ids[] = {
278 { .compatible = "qcom,msm-uartdm-v1.4" },
279 { }
280};
281
282U_BOOT_DRIVER(serial_msm) = {
283 .name = "serial_msm",
284 .id = UCLASS_SERIAL,
285 .of_match = msm_serial_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700286 .of_to_plat = msm_serial_of_to_plat,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700287 .priv_auto = sizeof(struct msm_serial_data),
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200288 .probe = msm_serial_probe,
289 .ops = &msm_serial_ops,
Caleb Connolly7a9c7b92024-02-26 17:26:12 +0000290 .flags = DM_FLAG_PRE_RELOC,
Mateusz Kulikowski8aac6972016-03-31 23:12:14 +0200291};
Caleb Connollya86d23a2024-02-26 17:26:11 +0000292
293#ifdef CONFIG_DEBUG_UART_MSM
294
295static struct msm_serial_data init_serial_data = {
296 .base = CONFIG_VAL(DEBUG_UART_BASE),
Caleb Connollyfb47e062024-04-15 16:03:40 +0100297 .clk_rate = CONFIG_VAL(DEBUG_UART_CLOCK),
Caleb Connollya86d23a2024-02-26 17:26:11 +0000298};
299
300#include <debug_uart.h>
301
302/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
303//int apq8016_clk_init_uart(phys_addr_t gcc_base);
304
305static inline void _debug_uart_init(void)
306{
307 /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
308 //apq8016_clk_init_uart(0x1800000);
309 uart_dm_init(&init_serial_data);
310}
311
312static inline void _debug_uart_putc(int ch)
313{
314 struct msm_serial_data *priv = &init_serial_data;
315
316 while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
317 !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
318 ;
319
320 writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
321
322 writel(1, priv->base + UARTDM_NCF_TX);
323 writel(ch, priv->base + UARTDM_TF);
324}
325
326DEBUG_UART_FUNCS
327
328#endif