wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * |
| 26 | * Configuration settings for the CU824 board. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | /* ------------------------------------------------------------------------- */ |
| 31 | |
| 32 | /* |
| 33 | * board/config.h - configuration options, board specific |
| 34 | */ |
| 35 | |
| 36 | #ifndef __CONFIG_H |
| 37 | #define __CONFIG_H |
| 38 | |
| 39 | /* |
| 40 | * High Level Configuration Options |
| 41 | * (easy to change) |
| 42 | */ |
| 43 | |
| 44 | #define CONFIG_MPC824X 1 |
| 45 | #define CONFIG_MPC8245 1 |
| 46 | #define CONFIG_BMW 1 |
| 47 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 48 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 49 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 50 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
| 51 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 52 | #define CONFIG_CONS_INDEX 1 |
| 53 | #define CONFIG_BAUDRATE 9600 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 55 | |
| 56 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
| 57 | |
| 58 | #define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */ |
| 59 | #define CONFIG_BOOTDELAY 5 |
| 60 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 62 | #define DOC_PASSIVE_PROBE 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 63 | #define CONFIG_SYS_DOC_SUPPORT_2000 1 |
| 64 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1 |
| 65 | #define CONFIG_SYS_DOC_SHORT_TIMEOUT 1 |
Jon Loeliger | 9261da0 | 2007-07-05 19:32:07 -0500 | [diff] [blame] | 66 | |
| 67 | |
| 68 | /* |
Jon Loeliger | f5709d1 | 2007-07-10 09:02:57 -0500 | [diff] [blame] | 69 | * BOOTP options |
| 70 | */ |
| 71 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 72 | #define CONFIG_BOOTP_BOOTPATH |
| 73 | #define CONFIG_BOOTP_GATEWAY |
| 74 | #define CONFIG_BOOTP_HOSTNAME |
| 75 | |
| 76 | |
| 77 | /* |
Jon Loeliger | 9261da0 | 2007-07-05 19:32:07 -0500 | [diff] [blame] | 78 | * Command line configuration. |
| 79 | */ |
| 80 | #include <config_cmd_default.h> |
| 81 | |
| 82 | #define CONFIG_CMD_DATE |
Jon Loeliger | 9261da0 | 2007-07-05 19:32:07 -0500 | [diff] [blame] | 83 | #define CONFIG_CMD_ELF |
Mike Frysinger | 2779cec | 2011-10-02 10:01:25 +0000 | [diff] [blame] | 84 | #undef CONFIG_CMD_NET |
| 85 | #undef CONFIG_CMD_NFS |
Jon Loeliger | 9261da0 | 2007-07-05 19:32:07 -0500 | [diff] [blame] | 86 | |
Bartlomiej Sieka | 582f1a3 | 2006-03-05 18:57:33 +0100 | [diff] [blame] | 87 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 88 | #if 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 89 | #define CONFIG_PCI 1 |
| 90 | #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ |
| 91 | #endif |
| 92 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 93 | /* |
| 94 | * Miscellaneous configurable options |
| 95 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 97 | #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ |
| 98 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 99 | |
| 100 | /* Print Buffer Size |
| 101 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 103 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 104 | #define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ |
| 105 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 106 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 107 | |
| 108 | /*----------------------------------------------------------------------- |
| 109 | * Start addresses for the final memory configuration |
| 110 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 112 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 114 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | #define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */ |
| 116 | #define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */ |
| 117 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
| 118 | #define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 119 | |
| 120 | /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the |
| 121 | * reset vector is actually located at FFB00100, but the 8245 |
| 122 | * takes care of us. |
| 123 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 127 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 129 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 130 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 131 | #define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 132 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
| 134 | #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 135 | |
| 136 | /* Maximum amount of RAM. |
| 137 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 139 | |
| 140 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
| 142 | #undef CONFIG_SYS_RAMBOOT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 143 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 144 | #define CONFIG_SYS_RAMBOOT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 145 | #endif |
| 146 | |
| 147 | |
| 148 | /*----------------------------------------------------------------------- |
| 149 | * Definitions for initial stack pointer and data area |
| 150 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 152 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 155 | |
| 156 | /* |
| 157 | * Low Level Configuration Settings |
| 158 | * (address mappings, register initial values, etc.) |
| 159 | * You should know what you are doing if you make changes here. |
| 160 | * For the detail description refer to the MPC8240 user's manual. |
| 161 | */ |
| 162 | |
| 163 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_HZ 1000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 165 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | #define CONFIG_SYS_ETH_DEV_FN 0x7800 |
| 167 | #define CONFIG_SYS_ETH_IOBASE 0x00104000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 168 | |
| 169 | /* Bit-field values for MCCR1. |
| 170 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_ROMNAL 0xf |
| 172 | #define CONFIG_SYS_ROMFAL 0x1f |
| 173 | #define CONFIG_SYS_DBUS_SIZE 0x3 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 174 | |
| 175 | /* Bit-field values for MCCR2. |
| 176 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ |
| 178 | #define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 179 | |
| 180 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. |
| 181 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | #define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 183 | |
| 184 | /* Bit-field values for MCCR3. |
| 185 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 187 | |
| 188 | /* Bit-field values for MCCR4. |
| 189 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */ |
| 191 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ |
| 192 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ |
| 193 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ |
| 194 | #define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */ |
| 195 | #define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */ |
| 196 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 197 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | #define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 199 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 201 | |
| 202 | /* Memory bank settings. |
| 203 | * Only bits 20-29 are actually used from these vales to set the |
| 204 | * start/end addresses. The upper two bits will always be 0, and the lower |
| 205 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end |
| 206 | * address. Refer to the MPC8240 book. |
| 207 | */ |
| 208 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_BANK0_START 0x00000000 |
| 210 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) |
| 211 | #define CONFIG_SYS_BANK0_ENABLE 1 |
| 212 | #define CONFIG_SYS_BANK1_START 0x3ff00000 |
| 213 | #define CONFIG_SYS_BANK1_END 0x3fffffff |
| 214 | #define CONFIG_SYS_BANK1_ENABLE 0 |
| 215 | #define CONFIG_SYS_BANK2_START 0x3ff00000 |
| 216 | #define CONFIG_SYS_BANK2_END 0x3fffffff |
| 217 | #define CONFIG_SYS_BANK2_ENABLE 0 |
| 218 | #define CONFIG_SYS_BANK3_START 0x3ff00000 |
| 219 | #define CONFIG_SYS_BANK3_END 0x3fffffff |
| 220 | #define CONFIG_SYS_BANK3_ENABLE 0 |
| 221 | #define CONFIG_SYS_BANK4_START 0x3ff00000 |
| 222 | #define CONFIG_SYS_BANK4_END 0x3fffffff |
| 223 | #define CONFIG_SYS_BANK4_ENABLE 0 |
| 224 | #define CONFIG_SYS_BANK5_START 0x3ff00000 |
| 225 | #define CONFIG_SYS_BANK5_END 0x3fffffff |
| 226 | #define CONFIG_SYS_BANK5_ENABLE 0 |
| 227 | #define CONFIG_SYS_BANK6_START 0x3ff00000 |
| 228 | #define CONFIG_SYS_BANK6_END 0x3fffffff |
| 229 | #define CONFIG_SYS_BANK6_ENABLE 0 |
| 230 | #define CONFIG_SYS_BANK7_START 0x3ff00000 |
| 231 | #define CONFIG_SYS_BANK7_END 0x3fffffff |
| 232 | #define CONFIG_SYS_BANK7_ENABLE 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 233 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_ODCR 0xff |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 235 | |
| 236 | #define CONFIG_PCI 1 /* Include PCI support */ |
| 237 | #undef CONFIG_PCI_PNP |
| 238 | |
| 239 | /* PCI Memory space(s) */ |
| 240 | #define PCI_MEM_SPACE1_START 0x80000000 |
| 241 | #define PCI_MEM_SPACE2_START 0xfd000000 |
| 242 | |
| 243 | /* ROM Spaces */ |
| 244 | #include "../board/bmw/bmw.h" |
| 245 | |
| 246 | /* BAT configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 248 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 249 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 250 | #define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 251 | #define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 252 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 253 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 254 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 255 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 256 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 257 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 258 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
| 260 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
| 261 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
| 262 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
| 263 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
| 264 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
| 265 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
| 266 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 267 | |
| 268 | /* |
| 269 | * For booting Linux, the board info and command line data |
| 270 | * have to be in the first 8 MB of memory, since this is |
| 271 | * the maximum mapped by the Linux kernel during initialization. |
| 272 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 273 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 274 | |
| 275 | /* |
| 276 | * FLASH organization |
| 277 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */ |
| 279 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 280 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 282 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 283 | |
| 284 | /* |
| 285 | * Warining: environment is not EMBEDDED in the U-Boot code. |
| 286 | * It's stored in flash separately. |
| 287 | */ |
Jean-Christophe PLAGNIOL-VILLARD | fdb79c3 | 2008-09-10 22:47:59 +0200 | [diff] [blame] | 288 | #define CONFIG_ENV_IS_IN_NVRAM 1 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 289 | #define CONFIG_ENV_OVERWRITE 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 290 | #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 291 | #define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */ |
| 292 | #define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */ |
| 293 | #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 294 | |
| 295 | /* |
| 296 | * Cache Configuration |
| 297 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 298 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
Jon Loeliger | 9261da0 | 2007-07-05 19:32:07 -0500 | [diff] [blame] | 299 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 300 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 301 | #endif |
| 302 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 303 | #endif /* __CONFIG_H */ |