blob: 8eeccdd4264fa77f0ecc93a508750e0c761fc377 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glassd2fdaaf2011-10-03 19:26:47 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
Simon Glassd2fdaaf2011-10-03 19:26:47 +00004 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
Simon Glasse7f1eb52013-06-11 11:14:44 -07009#ifdef FTRACE
10#define CONFIG_TRACE
Simon Glasse7f1eb52013-06-11 11:14:44 -070011#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
Simon Glass171bb992019-04-08 13:20:46 -060012#define CONFIG_TRACE_EARLY_SIZE (16 << 20)
Simon Glasse7f1eb52013-06-11 11:14:44 -070013#define CONFIG_TRACE_EARLY
14#define CONFIG_TRACE_EARLY_ADDR 0x00100000
Simon Glasse7f1eb52013-06-11 11:14:44 -070015#endif
16
Simon Glass1a4742c2016-07-04 11:57:52 -060017#ifndef CONFIG_SPL_BUILD
Simon Glass125a27b2014-06-11 23:29:43 -060018#define CONFIG_IO_TRACE
Simon Glass1a4742c2016-07-04 11:57:52 -060019#endif
Simon Glass125a27b2014-06-11 23:29:43 -060020
Thomas Chou7b059dc2015-10-30 15:35:52 +080021#ifndef CONFIG_TIMER
Rob Herring86bd4e82013-11-08 08:40:44 -060022#define CONFIG_SYS_TIMER_RATE 1000000
Thomas Chou7b059dc2015-10-30 15:35:52 +080023#endif
Rob Herring86bd4e82013-11-08 08:40:44 -060024
Henrik Nordström26f9a6c2013-11-10 10:26:56 -070025#define CONFIG_HOST_MAX_DEVICES 4
Simon Glasseb4cecd2012-12-26 09:53:37 +000026
Simon Glassd2fdaaf2011-10-03 19:26:47 +000027/*
Simon Glassc757cb02014-07-10 22:23:32 -060028 * Size of malloc() pool, before and after relocation
Simon Glassd2fdaaf2011-10-03 19:26:47 +000029 */
Simon Glassc757cb02014-07-10 22:23:32 -060030#define CONFIG_MALLOC_F_ADDR 0x0010000
Simon Glass7b89a1b2014-02-27 13:25:56 -070031#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
Simon Glassd2fdaaf2011-10-03 19:26:47 +000032
Simon Glassd2fdaaf2011-10-03 19:26:47 +000033#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
34
Simon Glassd2fdaaf2011-10-03 19:26:47 +000035/* turn on command-line edit/c/auto */
Simon Glassd2fdaaf2011-10-03 19:26:47 +000036
Simon Glass1f21d482014-09-15 06:33:20 -060037/* SPI - enable all SPI flash types for testing purposes */
Mike Frysinger494b82b2013-12-03 16:43:28 -070038
Simon Glassb3cbce22014-12-10 08:55:52 -070039#define CONFIG_I2C_EDID
Simon Glassb3cbce22014-12-10 08:55:52 -070040
Simon Glassd2fdaaf2011-10-03 19:26:47 +000041/* Memory things - we don't really want a memory test */
Simon Glassa081a0f2013-02-24 20:29:23 +000042#define CONFIG_SYS_LOAD_ADDR 0x00000000
Simon Glass84640e82014-02-27 13:26:25 -070043#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
44
45#define CONFIG_PHYSMEM
Simon Glassd2fdaaf2011-10-03 19:26:47 +000046
47/* Size of our emulated memory */
Heinrich Schuchardtfff251e2020-06-07 18:47:35 +020048#define SB_CONCAT(x, y) x ## y
49#define SB_TO_UL(s) SB_CONCAT(s, UL)
Simon Glass62cf9122013-04-26 02:53:43 +000050#define CONFIG_SYS_SDRAM_BASE 0
Heinrich Schuchardtfff251e2020-06-07 18:47:35 +020051#define CONFIG_SYS_SDRAM_SIZE \
52 (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
Simon Glass62cf9122013-04-26 02:53:43 +000053#define CONFIG_SYS_MONITOR_BASE 0
Simon Glassd2fdaaf2011-10-03 19:26:47 +000054
Simon Glassd2fdaaf2011-10-03 19:26:47 +000055#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
56 115200}
Simon Glassd2fdaaf2011-10-03 19:26:47 +000057
Sjoerd Simonsd0942242015-04-13 22:54:27 +020058#define BOOT_TARGET_DEVICES(func) \
59 func(HOST, host, 1) \
60 func(HOST, host, 0)
61
Simon Glass07bb5e72019-05-18 11:59:48 -060062#ifdef __ASSEMBLY__
63#define BOOTENV
64#else
Sjoerd Simonsd0942242015-04-13 22:54:27 +020065#include <config_distro_bootcmd.h>
Simon Glass07bb5e72019-05-18 11:59:48 -060066#endif
Simon Glassd2fdaaf2011-10-03 19:26:47 +000067
Joe Hershbergerc7dc2a32015-04-08 01:41:25 -050068#define CONFIG_KEEP_SERVERADDR
69#define CONFIG_UDP_CHECKSUM
Joe Hershbergerc7dc2a32015-04-08 01:41:25 -050070#define CONFIG_TIMESTAMP
Joe Hershbergerc96323f2015-03-22 17:09:22 -050071#define CONFIG_BOOTP_SERVERIP
Simon Glassd2fdaaf2011-10-03 19:26:47 +000072
Simon Glassdcc0bf42014-03-22 17:12:58 -060073#ifndef SANDBOX_NO_SDL
Simon Glass84640e82014-02-27 13:26:25 -070074#define CONFIG_SANDBOX_SDL
Simon Glassdcc0bf42014-03-22 17:12:58 -060075#endif
76
77/* LCD and keyboard require SDL support */
78#ifdef CONFIG_SANDBOX_SDL
Simon Glass84640e82014-02-27 13:26:25 -070079#define LCD_BPP LCD_COLOR16
Simon Glassf461f122014-10-15 04:53:04 -060080#define CONFIG_LCD_BMP_RLE8
Simon Glass84640e82014-02-27 13:26:25 -070081
Simon Glassdcc0bf42014-03-22 17:12:58 -060082#define CONFIG_KEYBOARD
83
Simon Glass2b510fa2015-11-08 23:48:07 -070084#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
Simon Glass798ff502016-01-21 19:44:51 -070085 "stdout=serial,vidconsole\0" \
86 "stderr=serial,vidconsole\0"
Simon Glassdcc0bf42014-03-22 17:12:58 -060087#else
Joe Hershberger6ab76992015-03-22 17:09:13 -050088#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
Simon Glass798ff502016-01-21 19:44:51 -070089 "stdout=serial,vidconsole\0" \
90 "stderr=serial,vidconsole\0"
Simon Glassdcc0bf42014-03-22 17:12:58 -060091#endif
Simon Glassd2fdaaf2011-10-03 19:26:47 +000092
Joe Hershberger6ab76992015-03-22 17:09:13 -050093#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
Claudiu Manoild9eaa922021-03-14 20:14:57 +080094 "eth2addr=00:00:11:22:33:48\0" \
Michael Walle7c41a222020-06-02 01:47:09 +020095 "eth3addr=00:00:11:22:33:45\0" \
Claudiu Manoild9eaa922021-03-14 20:14:57 +080096 "eth4addr=00:00:11:22:33:48\0" \
Michael Walle7c41a222020-06-02 01:47:09 +020097 "eth5addr=00:00:11:22:33:46\0" \
98 "eth6addr=00:00:11:22:33:47\0" \
Joe Hershberger6ab76992015-03-22 17:09:13 -050099 "ipaddr=1.2.3.4\0"
100
Sjoerd Simonsd0942242015-04-13 22:54:27 +0200101#define MEM_LAYOUT_ENV_SETTINGS \
102 "bootm_size=0x10000000\0" \
103 "kernel_addr_r=0x1000000\0" \
104 "fdt_addr_r=0xc00000\0" \
105 "ramdisk_addr_r=0x2000000\0" \
106 "scriptaddr=0x1000\0" \
107 "pxefile_addr_r=0x2000\0"
108
109#define CONFIG_EXTRA_ENV_SETTINGS \
110 SANDBOX_SERIAL_SETTINGS \
111 SANDBOX_ETH_SETTINGS \
112 BOOTENV \
113 MEM_LAYOUT_ENV_SETTINGS
Joe Hershberger6ab76992015-03-22 17:09:13 -0500114
Simon Glass1a4742c2016-07-04 11:57:52 -0600115#ifndef CONFIG_SPL_BUILD
Simon Glass4e7227c2016-05-01 11:36:23 -0600116#define CONFIG_SYS_IDE_MAXBUS 1
117#define CONFIG_SYS_ATA_IDE0_OFFSET 0
118#define CONFIG_SYS_IDE_MAXDEVICE 2
119#define CONFIG_SYS_ATA_BASE_ADDR 0x100
120#define CONFIG_SYS_ATA_DATA_OFFSET 0
121#define CONFIG_SYS_ATA_REG_OFFSET 1
122#define CONFIG_SYS_ATA_ALT_OFFSET 2
123#define CONFIG_SYS_ATA_STRIDE 4
Simon Glass1a4742c2016-07-04 11:57:52 -0600124#endif
Simon Glass4e7227c2016-05-01 11:36:23 -0600125
Simon Glass151b9352016-05-01 11:36:25 -0600126#define CONFIG_SCSI_AHCI_PLAT
127#define CONFIG_SYS_SCSI_MAX_DEVICE 2
128#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
129#define CONFIG_SYS_SCSI_MAX_LUN 4
130
Simon Glass4a63e332016-05-01 11:36:27 -0600131#define CONFIG_SYS_SATA_MAX_DEVICE 2
132
Simon Glassd2fdaaf2011-10-03 19:26:47 +0000133#endif