blob: c95fcee9f6c8880812341bf5b64de304201813f8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbellb2765ec2014-05-05 11:52:24 +01002/*
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Tom Cubie <tangliang@allwinnertech.com>
Ian Campbellb2765ec2014-05-05 11:52:24 +01006 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/gpio.h>
11
Simon Glassd8624532014-10-30 20:25:47 -060012void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
Ian Campbellb2765ec2014-05-05 11:52:24 +010013{
Simon Glassd8624532014-10-30 20:25:47 -060014 u32 index = GPIO_CFG_INDEX(bank_offset);
15 u32 offset = GPIO_CFG_OFFSET(bank_offset);
Ian Campbellb2765ec2014-05-05 11:52:24 +010016
Andre Przywara8a4184c2022-01-30 01:19:42 +000017 clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
Ian Campbellb2765ec2014-05-05 11:52:24 +010018}
19
Simon Glassd8624532014-10-30 20:25:47 -060020void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
Ian Campbellb2765ec2014-05-05 11:52:24 +010021{
Ian Campbellb2765ec2014-05-05 11:52:24 +010022 u32 bank = GPIO_BANK(pin);
Ian Campbellb2765ec2014-05-05 11:52:24 +010023 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
24
Simon Glassd8624532014-10-30 20:25:47 -060025 sunxi_gpio_set_cfgbank(pio, pin, val);
26}
27
28int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
29{
30 u32 index = GPIO_CFG_INDEX(bank_offset);
31 u32 offset = GPIO_CFG_OFFSET(bank_offset);
32 u32 cfg;
33
Andre Przywara8a4184c2022-01-30 01:19:42 +000034 cfg = readl(&pio->cfg[index]);
Ian Campbellb2765ec2014-05-05 11:52:24 +010035 cfg >>= offset;
36
37 return cfg & 0xf;
38}
39
Simon Glassd8624532014-10-30 20:25:47 -060040int sunxi_gpio_get_cfgpin(u32 pin)
41{
42 u32 bank = GPIO_BANK(pin);
43 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
44
45 return sunxi_gpio_get_cfgbank(pio, pin);
46}
47
Samuel Holland41abadc2021-10-20 23:52:54 -050048void sunxi_gpio_set_drv(u32 pin, u32 val)
Ian Campbellb2765ec2014-05-05 11:52:24 +010049{
50 u32 bank = GPIO_BANK(pin);
Ian Campbellb2765ec2014-05-05 11:52:24 +010051 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
52
Samuel Holland6dde4a22021-10-20 23:52:55 -050053 sunxi_gpio_set_drv_bank(pio, pin, val);
54}
55
56void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
57{
58 u32 index = GPIO_DRV_INDEX(bank_offset);
59 u32 offset = GPIO_DRV_OFFSET(bank_offset);
60
Andre Przywara8a4184c2022-01-30 01:19:42 +000061 clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
Ian Campbellb2765ec2014-05-05 11:52:24 +010062}
63
Samuel Holland41abadc2021-10-20 23:52:54 -050064void sunxi_gpio_set_pull(u32 pin, u32 val)
Ian Campbellb2765ec2014-05-05 11:52:24 +010065{
66 u32 bank = GPIO_BANK(pin);
Ian Campbellb2765ec2014-05-05 11:52:24 +010067 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
68
Samuel Holland6dde4a22021-10-20 23:52:55 -050069 sunxi_gpio_set_pull_bank(pio, pin, val);
70}
71
72void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
73{
74 u32 index = GPIO_PULL_INDEX(bank_offset);
75 u32 offset = GPIO_PULL_OFFSET(bank_offset);
76
Andre Przywara8a4184c2022-01-30 01:19:42 +000077 clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset);
Ian Campbellb2765ec2014-05-05 11:52:24 +010078}