Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2011 |
| 4 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 5 | * Tom Cubie <tangliang@allwinnertech.com> |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/gpio.h> |
| 11 | |
Simon Glass | d862453 | 2014-10-30 20:25:47 -0600 | [diff] [blame] | 12 | void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 13 | { |
Simon Glass | d862453 | 2014-10-30 20:25:47 -0600 | [diff] [blame] | 14 | u32 index = GPIO_CFG_INDEX(bank_offset); |
| 15 | u32 offset = GPIO_CFG_OFFSET(bank_offset); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 16 | |
Andre Przywara | 8a4184c | 2022-01-30 01:19:42 +0000 | [diff] [blame] | 17 | clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 18 | } |
| 19 | |
Simon Glass | d862453 | 2014-10-30 20:25:47 -0600 | [diff] [blame] | 20 | void sunxi_gpio_set_cfgpin(u32 pin, u32 val) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 21 | { |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 22 | u32 bank = GPIO_BANK(pin); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 23 | struct sunxi_gpio *pio = BANK_TO_GPIO(bank); |
| 24 | |
Simon Glass | d862453 | 2014-10-30 20:25:47 -0600 | [diff] [blame] | 25 | sunxi_gpio_set_cfgbank(pio, pin, val); |
| 26 | } |
| 27 | |
| 28 | int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) |
| 29 | { |
| 30 | u32 index = GPIO_CFG_INDEX(bank_offset); |
| 31 | u32 offset = GPIO_CFG_OFFSET(bank_offset); |
| 32 | u32 cfg; |
| 33 | |
Andre Przywara | 8a4184c | 2022-01-30 01:19:42 +0000 | [diff] [blame] | 34 | cfg = readl(&pio->cfg[index]); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 35 | cfg >>= offset; |
| 36 | |
| 37 | return cfg & 0xf; |
| 38 | } |
| 39 | |
Simon Glass | d862453 | 2014-10-30 20:25:47 -0600 | [diff] [blame] | 40 | int sunxi_gpio_get_cfgpin(u32 pin) |
| 41 | { |
| 42 | u32 bank = GPIO_BANK(pin); |
| 43 | struct sunxi_gpio *pio = BANK_TO_GPIO(bank); |
| 44 | |
| 45 | return sunxi_gpio_get_cfgbank(pio, pin); |
| 46 | } |
| 47 | |
Samuel Holland | 41abadc | 2021-10-20 23:52:54 -0500 | [diff] [blame] | 48 | void sunxi_gpio_set_drv(u32 pin, u32 val) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 49 | { |
| 50 | u32 bank = GPIO_BANK(pin); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 51 | struct sunxi_gpio *pio = BANK_TO_GPIO(bank); |
| 52 | |
Samuel Holland | 6dde4a2 | 2021-10-20 23:52:55 -0500 | [diff] [blame] | 53 | sunxi_gpio_set_drv_bank(pio, pin, val); |
| 54 | } |
| 55 | |
| 56 | void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) |
| 57 | { |
| 58 | u32 index = GPIO_DRV_INDEX(bank_offset); |
| 59 | u32 offset = GPIO_DRV_OFFSET(bank_offset); |
| 60 | |
Andre Przywara | 8a4184c | 2022-01-30 01:19:42 +0000 | [diff] [blame] | 61 | clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 62 | } |
| 63 | |
Samuel Holland | 41abadc | 2021-10-20 23:52:54 -0500 | [diff] [blame] | 64 | void sunxi_gpio_set_pull(u32 pin, u32 val) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 65 | { |
| 66 | u32 bank = GPIO_BANK(pin); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 67 | struct sunxi_gpio *pio = BANK_TO_GPIO(bank); |
| 68 | |
Samuel Holland | 6dde4a2 | 2021-10-20 23:52:55 -0500 | [diff] [blame] | 69 | sunxi_gpio_set_pull_bank(pio, pin, val); |
| 70 | } |
| 71 | |
| 72 | void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) |
| 73 | { |
| 74 | u32 index = GPIO_PULL_INDEX(bank_offset); |
| 75 | u32 offset = GPIO_PULL_OFFSET(bank_offset); |
| 76 | |
Andre Przywara | 8a4184c | 2022-01-30 01:19:42 +0000 | [diff] [blame] | 77 | clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 78 | } |