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Kumar Gala124b0822008-08-26 15:01:29 -05001/*
York Sun2896cb72014-03-27 17:54:47 -07002 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala124b0822008-08-26 15:01:29 -05003 *
Tom Rinie2378802016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Kumar Gala124b0822008-08-26 15:01:29 -05005 */
6
7#ifndef FSL_DDR_MEMCTL_H
8#define FSL_DDR_MEMCTL_H
9
10/*
11 * Pick a basic DDR Technology.
12 */
13#include <ddr_spd.h>
York Sun2896cb72014-03-27 17:54:47 -070014#include <fsl_ddrc_version.h>
Kumar Gala124b0822008-08-26 15:01:29 -050015
York Sun2896cb72014-03-27 17:54:47 -070016#define SDRAM_TYPE_DDR1 2
17#define SDRAM_TYPE_DDR2 3
18#define SDRAM_TYPE_LPDDR1 6
19#define SDRAM_TYPE_DDR3 7
20#define SDRAM_TYPE_DDR4 5
Kumar Gala124b0822008-08-26 15:01:29 -050021
Dave Liu4be87b22009-03-14 12:48:30 +080022#define DDR_BL4 4 /* burst length 4 */
23#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
24#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
25#define DDR_BL8 8 /* burst length 8 */
26
York Sunba0c2eb2011-01-10 12:03:00 +000027#define DDR3_RTT_OFF 0
Dave Liu04899192010-03-05 12:23:00 +080028#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
29#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
30#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
31#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
32#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
33
York Sun5cb12f62015-11-04 10:03:17 -080034#define DDR4_RTT_OFF 0
35#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
36#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
37#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
38#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
39#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
40#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
41#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
42
York Sun454f5072011-08-26 11:32:43 -070043#define DDR2_RTT_OFF 0
44#define DDR2_RTT_75_OHM 1
45#define DDR2_RTT_150_OHM 2
46#define DDR2_RTT_50_OHM 3
47
York Sunf0626592013-09-30 09:22:09 -070048#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala124b0822008-08-26 15:01:29 -050049#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
50typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
51#ifndef CONFIG_FSL_SDRAM_TYPE
52#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
53#endif
York Sunf0626592013-09-30 09:22:09 -070054#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala124b0822008-08-26 15:01:29 -050055#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
56typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
57#ifndef CONFIG_FSL_SDRAM_TYPE
58#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
59#endif
York Sunf0626592013-09-30 09:22:09 -070060#elif defined(CONFIG_SYS_FSL_DDR3)
Kumar Gala124b0822008-08-26 15:01:29 -050061typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
Dave Liu4758d532008-11-21 16:31:29 +080062#ifndef CONFIG_FSL_SDRAM_TYPE
63#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
Kumar Gala124b0822008-08-26 15:01:29 -050064#endif
York Sun2896cb72014-03-27 17:54:47 -070065#elif defined(CONFIG_SYS_FSL_DDR4)
66#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
67typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
68#ifndef CONFIG_FSL_SDRAM_TYPE
69#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
70#endif
York Sunf0626592013-09-30 09:22:09 -070071#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
Kumar Gala124b0822008-08-26 15:01:29 -050072
York Sunba0c2eb2011-01-10 12:03:00 +000073#define FSL_DDR_ODT_NEVER 0x0
74#define FSL_DDR_ODT_CS 0x1
75#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
76#define FSL_DDR_ODT_OTHER_DIMM 0x3
77#define FSL_DDR_ODT_ALL 0x4
78#define FSL_DDR_ODT_SAME_DIMM 0x5
79#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
80#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
81
Haiying Wang272b5962008-10-03 12:36:39 -040082/* define bank(chip select) interleaving mode */
83#define FSL_DDR_CS0_CS1 0x40
84#define FSL_DDR_CS2_CS3 0x20
85#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
86#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
87
88/* define memory controller interleaving mode */
89#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
90#define FSL_DDR_PAGE_INTERLEAVING 0x1
91#define FSL_DDR_BANK_INTERLEAVING 0x2
92#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
York Sunc459ae62014-02-10 13:59:44 -080093#define FSL_DDR_256B_INTERLEAVING 0x8
York Sune8dc17b2012-08-17 08:22:39 +000094#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
95#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
96#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
97/* placeholder for 4-way interleaving */
98#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
99#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
100#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
Haiying Wang272b5962008-10-03 12:36:39 -0400101
York Sun98df4d12012-10-08 07:44:23 +0000102#define SDRAM_CS_CONFIG_EN 0x80000000
103
Poonam_Aggrwal-b1081230cb1452009-01-04 08:46:38 +0530104/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
105 */
106#define SDRAM_CFG_MEM_EN 0x80000000
107#define SDRAM_CFG_SREN 0x40000000
108#define SDRAM_CFG_ECC_EN 0x20000000
109#define SDRAM_CFG_RD_EN 0x10000000
110#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
111#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
112#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
113#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
114#define SDRAM_CFG_DYN_PWR 0x00200000
Matthew McClintock78fb1752012-08-13 08:10:37 +0000115#define SDRAM_CFG_DBW_MASK 0x00180000
York Sun016095d2012-10-08 07:44:24 +0000116#define SDRAM_CFG_DBW_SHIFT 19
Poonam_Aggrwal-b1081230cb1452009-01-04 08:46:38 +0530117#define SDRAM_CFG_32_BE 0x00080000
Poonam Aggrwal42d36402011-02-07 15:09:51 +0530118#define SDRAM_CFG_16_BE 0x00100000
Poonam_Aggrwal-b1081230cb1452009-01-04 08:46:38 +0530119#define SDRAM_CFG_8_BE 0x00040000
120#define SDRAM_CFG_NCAP 0x00020000
121#define SDRAM_CFG_2T_EN 0x00008000
122#define SDRAM_CFG_BI 0x00000001
123
Tang Yuantian064f1262014-11-21 11:17:15 +0800124#define SDRAM_CFG2_FRC_SR 0x80000000
York Sunc8fc9592011-01-25 22:05:49 -0800125#define SDRAM_CFG2_D_INIT 0x00000010
Shengzhou Liu52199442016-03-10 17:36:56 +0800126#define SDRAM_CFG2_AP_EN 0x00000020
York Sunc8fc9592011-01-25 22:05:49 -0800127#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
York Sun15f874a2011-08-26 11:32:40 -0700128#define SDRAM_CFG2_ODT_NEVER 0
129#define SDRAM_CFG2_ODT_ONLY_WRITE 1
130#define SDRAM_CFG2_ODT_ONLY_READ 2
131#define SDRAM_CFG2_ODT_ALWAYS 3
York Sunc8fc9592011-01-25 22:05:49 -0800132
Shengzhou Liubdda96c2015-12-16 16:45:41 +0800133#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
York Sunc8fc9592011-01-25 22:05:49 -0800134#define TIMING_CFG_2_CPO_MASK 0x0F800000
135
York Sun2896cb72014-03-27 17:54:47 -0700136#if defined(CONFIG_SYS_FSL_DDR_VER) && \
137 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
Dave Liu4be87b22009-03-14 12:48:30 +0800138#define RD_TO_PRE_MASK 0xf
139#define RD_TO_PRE_SHIFT 13
140#define WR_DATA_DELAY_MASK 0xf
141#define WR_DATA_DELAY_SHIFT 9
142#else
143#define RD_TO_PRE_MASK 0x7
144#define RD_TO_PRE_SHIFT 13
145#define WR_DATA_DELAY_MASK 0x7
146#define WR_DATA_DELAY_SHIFT 10
147#endif
148
Shengzhou Liuddf060b2016-04-07 16:22:21 +0800149/* DDR_EOR register */
150#define DDR_EOR_RD_REOD_DIS 0x07000000
151#define DDR_EOR_WD_REOD_DIS 0x00100000
152
York Sun922f40f2011-01-10 12:03:01 +0000153/* DDR_MD_CNTL */
154#define MD_CNTL_MD_EN 0x80000000
155#define MD_CNTL_CS_SEL_CS0 0x00000000
156#define MD_CNTL_CS_SEL_CS1 0x10000000
157#define MD_CNTL_CS_SEL_CS2 0x20000000
158#define MD_CNTL_CS_SEL_CS3 0x30000000
159#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
160#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
161#define MD_CNTL_MD_SEL_MR 0x00000000
162#define MD_CNTL_MD_SEL_EMR 0x01000000
163#define MD_CNTL_MD_SEL_EMR2 0x02000000
164#define MD_CNTL_MD_SEL_EMR3 0x03000000
165#define MD_CNTL_SET_REF 0x00800000
166#define MD_CNTL_SET_PRE 0x00400000
167#define MD_CNTL_CKE_CNTL_LOW 0x00100000
168#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
169#define MD_CNTL_WRCW 0x00080000
170#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
York Sun1f8d7062015-03-19 09:30:29 -0700171#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
172#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
York Sun922f40f2011-01-10 12:03:01 +0000173
York Sun00a69c02011-01-10 12:03:02 +0000174/* DDR_CDR1 */
175#define DDR_CDR1_DHC_EN 0x80000000
York Sun7d69ea32012-10-08 07:44:22 +0000176#define DDR_CDR1_ODT_SHIFT 17
177#define DDR_CDR1_ODT_MASK 0x6
178#define DDR_CDR2_ODT_MASK 0x1
179#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
180#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
York Sun2896cb72014-03-27 17:54:47 -0700181#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
Tang Yuantian064f1262014-11-21 11:17:15 +0800182#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
York Sun03017032015-03-20 19:28:23 -0700183#define DDR_CDR2_VREF_RANGE_2 0x00000040
York Sun7d69ea32012-10-08 07:44:22 +0000184
Shengzhou Liu52199442016-03-10 17:36:56 +0800185/* DDR ERR_DISABLE */
186#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
187
188/* Mode Registers */
189#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
190#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
191
Shengzhou Liu9c3cdc22016-03-16 13:50:23 +0800192/* DEBUG_26 register */
193#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
194#define DDR_CAS_TO_PRE_SUB_SHIFT 12
195
Shengzhou Liub2dee262016-03-16 13:50:22 +0800196/* DEBUG_29 register */
197#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
198
Shengzhou Liu52199442016-03-10 17:36:56 +0800199
York Sun7d69ea32012-10-08 07:44:22 +0000200#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
201 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
York Sun2896cb72014-03-27 17:54:47 -0700202#ifdef CONFIG_SYS_FSL_DDR3L
203#define DDR_CDR_ODT_OFF 0x0
204#define DDR_CDR_ODT_120ohm 0x1
205#define DDR_CDR_ODT_200ohm 0x2
206#define DDR_CDR_ODT_75ohm 0x3
207#define DDR_CDR_ODT_60ohm 0x5
208#define DDR_CDR_ODT_46ohm 0x7
209#elif defined(CONFIG_SYS_FSL_DDR4)
210#define DDR_CDR_ODT_OFF 0x0
211#define DDR_CDR_ODT_100ohm 0x1
212#define DDR_CDR_ODT_120OHM 0x2
213#define DDR_CDR_ODT_80ohm 0x3
214#define DDR_CDR_ODT_60ohm 0x4
215#define DDR_CDR_ODT_40ohm 0x5
216#define DDR_CDR_ODT_50ohm 0x6
217#define DDR_CDR_ODT_30ohm 0x7
218#else
York Sun7d69ea32012-10-08 07:44:22 +0000219#define DDR_CDR_ODT_OFF 0x0
220#define DDR_CDR_ODT_120ohm 0x1
221#define DDR_CDR_ODT_180ohm 0x2
222#define DDR_CDR_ODT_75ohm 0x3
223#define DDR_CDR_ODT_110ohm 0x4
224#define DDR_CDR_ODT_60hm 0x5
225#define DDR_CDR_ODT_70ohm 0x6
226#define DDR_CDR_ODT_47ohm 0x7
York Sun2896cb72014-03-27 17:54:47 -0700227#endif /* DDR3L */
York Sun7d69ea32012-10-08 07:44:22 +0000228#else
229#define DDR_CDR_ODT_75ohm 0x0
230#define DDR_CDR_ODT_55ohm 0x1
231#define DDR_CDR_ODT_60ohm 0x2
232#define DDR_CDR_ODT_50ohm 0x3
233#define DDR_CDR_ODT_150ohm 0x4
234#define DDR_CDR_ODT_43ohm 0x5
235#define DDR_CDR_ODT_120ohm 0x6
236#endif
York Sun00a69c02011-01-10 12:03:02 +0000237
Tang Yuantian064f1262014-11-21 11:17:15 +0800238#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
239
Kumar Gala124b0822008-08-26 15:01:29 -0500240/* Record of register values computed */
241typedef struct fsl_ddr_cfg_regs_s {
242 struct {
243 unsigned int bnds;
244 unsigned int config;
245 unsigned int config_2;
246 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
247 unsigned int timing_cfg_3;
248 unsigned int timing_cfg_0;
249 unsigned int timing_cfg_1;
250 unsigned int timing_cfg_2;
251 unsigned int ddr_sdram_cfg;
252 unsigned int ddr_sdram_cfg_2;
York Sun2896cb72014-03-27 17:54:47 -0700253 unsigned int ddr_sdram_cfg_3;
Kumar Gala124b0822008-08-26 15:01:29 -0500254 unsigned int ddr_sdram_mode;
255 unsigned int ddr_sdram_mode_2;
York Sunba0c2eb2011-01-10 12:03:00 +0000256 unsigned int ddr_sdram_mode_3;
257 unsigned int ddr_sdram_mode_4;
258 unsigned int ddr_sdram_mode_5;
259 unsigned int ddr_sdram_mode_6;
260 unsigned int ddr_sdram_mode_7;
261 unsigned int ddr_sdram_mode_8;
York Sun2896cb72014-03-27 17:54:47 -0700262 unsigned int ddr_sdram_mode_9;
263 unsigned int ddr_sdram_mode_10;
264 unsigned int ddr_sdram_mode_11;
265 unsigned int ddr_sdram_mode_12;
266 unsigned int ddr_sdram_mode_13;
267 unsigned int ddr_sdram_mode_14;
268 unsigned int ddr_sdram_mode_15;
269 unsigned int ddr_sdram_mode_16;
Kumar Gala124b0822008-08-26 15:01:29 -0500270 unsigned int ddr_sdram_md_cntl;
271 unsigned int ddr_sdram_interval;
272 unsigned int ddr_data_init;
273 unsigned int ddr_sdram_clk_cntl;
274 unsigned int ddr_init_addr;
275 unsigned int ddr_init_ext_addr;
276 unsigned int timing_cfg_4;
277 unsigned int timing_cfg_5;
York Sun2896cb72014-03-27 17:54:47 -0700278 unsigned int timing_cfg_6;
279 unsigned int timing_cfg_7;
280 unsigned int timing_cfg_8;
281 unsigned int timing_cfg_9;
Kumar Gala124b0822008-08-26 15:01:29 -0500282 unsigned int ddr_zq_cntl;
283 unsigned int ddr_wrlvl_cntl;
York Sun7d69ea32012-10-08 07:44:22 +0000284 unsigned int ddr_wrlvl_cntl_2;
285 unsigned int ddr_wrlvl_cntl_3;
Kumar Gala124b0822008-08-26 15:01:29 -0500286 unsigned int ddr_sr_cntr;
287 unsigned int ddr_sdram_rcw_1;
288 unsigned int ddr_sdram_rcw_2;
York Sun2896cb72014-03-27 17:54:47 -0700289 unsigned int ddr_sdram_rcw_3;
290 unsigned int ddr_sdram_rcw_4;
291 unsigned int ddr_sdram_rcw_5;
292 unsigned int ddr_sdram_rcw_6;
293 unsigned int dq_map_0;
294 unsigned int dq_map_1;
295 unsigned int dq_map_2;
296 unsigned int dq_map_3;
york42603722010-07-02 22:25:54 +0000297 unsigned int ddr_eor;
York Sun7dda8472011-01-10 12:02:59 +0000298 unsigned int ddr_cdr1;
299 unsigned int ddr_cdr2;
300 unsigned int err_disable;
301 unsigned int err_int_en;
York Sun7c725782016-08-29 17:04:12 +0800302 unsigned int debug[64];
Kumar Gala124b0822008-08-26 15:01:29 -0500303} fsl_ddr_cfg_regs_t;
304
305typedef struct memctl_options_partial_s {
Priyanka Jain4a717412013-09-25 10:41:19 +0530306 unsigned int all_dimms_ecc_capable;
307 unsigned int all_dimms_tckmax_ps;
308 unsigned int all_dimms_burst_lengths_bitmask;
309 unsigned int all_dimms_registered;
310 unsigned int all_dimms_unbuffered;
York Sun2896cb72014-03-27 17:54:47 -0700311 /* unsigned int lowest_common_spd_caslat; */
Priyanka Jain4a717412013-09-25 10:41:19 +0530312 unsigned int all_dimms_minimum_trcd_ps;
Kumar Gala124b0822008-08-26 15:01:29 -0500313} memctl_options_partial_t;
314
York Sundd803dd2011-05-27 07:25:51 +0800315#define DDR_DATA_BUS_WIDTH_64 0
316#define DDR_DATA_BUS_WIDTH_32 1
317#define DDR_DATA_BUS_WIDTH_16 2
York Sune0f60462014-09-05 13:52:43 +0800318#define DDR_CSWL_CS0 0x04000001
Kumar Gala124b0822008-08-26 15:01:29 -0500319/*
320 * Generalized parameters for memory controller configuration,
321 * might be a little specific to the FSL memory controller
322 */
323typedef struct memctl_options_s {
324 /*
325 * Memory organization parameters
326 *
327 * if DIMM is present in the system
328 * where DIMMs are with respect to chip select
329 * where chip selects are with respect to memory boundaries
330 */
331 unsigned int registered_dimm_en; /* use registered DIMM support */
332
333 /* Options local to a Chip Select */
334 struct cs_local_opts_s {
335 unsigned int auto_precharge;
336 unsigned int odt_rd_cfg;
337 unsigned int odt_wr_cfg;
York Sunba0c2eb2011-01-10 12:03:00 +0000338 unsigned int odt_rtt_norm;
339 unsigned int odt_rtt_wr;
Kumar Gala124b0822008-08-26 15:01:29 -0500340 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
341
342 /* Special configurations for chip select */
343 unsigned int memctl_interleaving;
344 unsigned int memctl_interleaving_mode;
345 unsigned int ba_intlv_ctl;
york42603722010-07-02 22:25:54 +0000346 unsigned int addr_hash;
Kumar Gala124b0822008-08-26 15:01:29 -0500347
348 /* Operational mode parameters */
Priyanka Jain4a717412013-09-25 10:41:19 +0530349 unsigned int ecc_mode; /* Use ECC? */
Kumar Gala124b0822008-08-26 15:01:29 -0500350 /* Initialize ECC using memory controller? */
Priyanka Jain4a717412013-09-25 10:41:19 +0530351 unsigned int ecc_init_using_memctl;
352 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
Kumar Gala124b0822008-08-26 15:01:29 -0500353 /* SREN - self-refresh during sleep */
354 unsigned int self_refresh_in_sleep;
Joakim Tjernlund6dc192d2015-10-14 16:32:00 +0200355 /* SR_IE - Self-refresh interrupt enable */
356 unsigned int self_refresh_interrupt_en;
Kumar Gala124b0822008-08-26 15:01:29 -0500357 unsigned int dynamic_power; /* DYN_PWR */
358 /* memory data width to use (16-bit, 32-bit, 64-bit) */
359 unsigned int data_bus_width;
Dave Liu4be87b22009-03-14 12:48:30 +0800360 unsigned int burst_length; /* BL4, OTF and BL8 */
361 /* On-The-Fly Burst Chop enable */
Priyanka Jain4a717412013-09-25 10:41:19 +0530362 unsigned int otf_burst_chop_en;
Dave Liu4be87b22009-03-14 12:48:30 +0800363 /* mirrior DIMMs for DDR3 */
364 unsigned int mirrored_dimm;
yorkf4f93c62010-07-02 22:25:53 +0000365 unsigned int quad_rank_present;
Shengzhou Liu52199442016-03-10 17:36:56 +0800366 unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
York Sun4889c982013-06-25 11:37:47 -0700367 unsigned int x4_en; /* enable x4 devices */
Kumar Gala124b0822008-08-26 15:01:29 -0500368
369 /* Global Timing Parameters */
370 unsigned int cas_latency_override;
371 unsigned int cas_latency_override_value;
372 unsigned int use_derated_caslat;
373 unsigned int additive_latency_override;
374 unsigned int additive_latency_override_value;
375
376 unsigned int clk_adjust; /* */
377 unsigned int cpo_override;
378 unsigned int write_data_delay; /* DQS adjust */
Dave Liu64ee7df2009-12-16 10:24:37 -0600379
York Sune0f60462014-09-05 13:52:43 +0800380 unsigned int cswl_override;
Dave Liu64ee7df2009-12-16 10:24:37 -0600381 unsigned int wrlvl_override;
382 unsigned int wrlvl_sample; /* Write leveling */
383 unsigned int wrlvl_start;
York Sun7d69ea32012-10-08 07:44:22 +0000384 unsigned int wrlvl_ctl_2;
385 unsigned int wrlvl_ctl_3;
Dave Liu64ee7df2009-12-16 10:24:37 -0600386
Kumar Gala124b0822008-08-26 15:01:29 -0500387 unsigned int half_strength_driver_enable;
Priyanka Jain4a717412013-09-25 10:41:19 +0530388 unsigned int twot_en;
389 unsigned int threet_en;
Kumar Gala124b0822008-08-26 15:01:29 -0500390 unsigned int bstopre;
Priyanka Jain4a717412013-09-25 10:41:19 +0530391 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
Dave Liu2aad0ae2008-11-21 16:31:35 +0800392
Dave Liu4be87b22009-03-14 12:48:30 +0800393 /* Rtt impedance */
394 unsigned int rtt_override; /* rtt_override enable */
395 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
Dave Liu2d0f1252009-12-16 10:24:38 -0600396 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
Dave Liu4be87b22009-03-14 12:48:30 +0800397
Dave Liu2aad0ae2008-11-21 16:31:35 +0800398 /* Automatic self refresh */
399 unsigned int auto_self_refresh_en;
400 unsigned int sr_it;
Dave Liu4be87b22009-03-14 12:48:30 +0800401 /* ZQ calibration */
402 unsigned int zq_en;
403 /* Write leveling */
404 unsigned int wrlvl_en;
York Sun7dda8472011-01-10 12:02:59 +0000405 /* RCW override for RDIMM */
406 unsigned int rcw_override;
407 unsigned int rcw_1;
408 unsigned int rcw_2;
409 /* control register 1 */
410 unsigned int ddr_cdr1;
York Sun7d69ea32012-10-08 07:44:22 +0000411 unsigned int ddr_cdr2;
York Sunf8691fc2011-05-27 13:44:28 +0800412
413 unsigned int trwt_override;
414 unsigned int trwt; /* read-to-write turnaround */
Kumar Gala124b0822008-08-26 15:01:29 -0500415} memctl_options_t;
416
York Sun79a779b2014-08-01 15:51:00 -0700417phys_size_t fsl_ddr_sdram(void);
418phys_size_t fsl_ddr_sdram_size(void);
419phys_size_t fsl_other_ddr_sdram(unsigned long long base,
420 unsigned int first_ctrl,
421 unsigned int num_ctrls,
422 unsigned int dimm_slots_per_ctrl,
423 int (*board_need_reset)(void),
424 void (*board_reset)(void),
425 void (*board_de_reset)(void));
Kumar Galaf582d982011-01-09 14:06:28 -0600426extern int fsl_use_spd(void);
York Sun79a779b2014-08-01 15:51:00 -0700427void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
428 unsigned int ctrl_num, int step);
York Sun016095d2012-10-08 07:44:24 +0000429u32 fsl_ddr_get_intl3r(void);
York Sun79a779b2014-08-01 15:51:00 -0700430void print_ddr_info(unsigned int start_ctrl);
York Sun269c7eb2010-10-18 13:46:49 -0700431
York Sun5e155552013-06-25 11:37:48 -0700432static void __board_assert_mem_reset(void)
433{
434}
435
436static void __board_deassert_mem_reset(void)
437{
438}
439
440void board_assert_mem_reset(void)
441 __attribute__((weak, alias("__board_assert_mem_reset")));
442
443void board_deassert_mem_reset(void)
444 __attribute__((weak, alias("__board_deassert_mem_reset")));
445
446static int __board_need_mem_reset(void)
447{
448 return 0;
449}
450
451int board_need_mem_reset(void)
452 __attribute__((weak, alias("__board_need_mem_reset")));
453
Tang Yuantian064f1262014-11-21 11:17:15 +0800454#if defined(CONFIG_DEEP_SLEEP)
455void board_mem_sleep_setup(void);
456bool is_warm_boot(void);
457int fsl_dp_resume(void);
458#endif
Tang Yuantiana7364af2014-04-17 15:33:46 +0800459
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600460/*
461 * The 85xx boards have a common prototype for fixed_sdram so put the
462 * declaration here.
463 */
464#ifdef CONFIG_MPC85xx
465extern phys_size_t fixed_sdram(void);
466#endif
467
468#if defined(CONFIG_DDR_ECC)
469extern void ddr_enable_ecc(unsigned int dram_size);
470#endif
471
472
York Sun269c7eb2010-10-18 13:46:49 -0700473typedef struct fixed_ddr_parm{
474 int min_freq;
475 int max_freq;
476 fsl_ddr_cfg_regs_t *ddr_settings;
477} fixed_ddr_parm_t;
Kumar Gala124b0822008-08-26 15:01:29 -0500478#endif