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git01.mediatek.com / filogic / uboot / fac4ced66ece9fe0e8c81968f91ea0809de9009f / . / board / nvidia / jetson-tk1 / pinmux-config-jetson-tk1.h
blob: 01237dbc29122dd3e3c2cafc10bedb24ed17816f [file] [log] [blame]
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]1/*
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Stephen Warren093b9652015-07-30 14:34:09 -0600[diff] [blame]7/*
8 * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
9 *
10 * To generate this file, use the tegra-pinmux-scripts tool available from
11 * https://github.com/NVIDIA/tegra-pinmux-scripts
12 * Run "board-to-uboot.py jetson-tk1".
13 */
14
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]15#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
16#define _PINMUX_CONFIG_JETSON_TK1_H_
17
Stephen Warren7f20bb22016-05-12 12:07:39 -0600[diff] [blame]18#define GPIO_INIT(_port, _gpio, _init) \
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]19 { \
Stephen Warren7f20bb22016-05-12 12:07:39 -0600[diff] [blame]20 .gpio = TEGRA_GPIO(_port, _gpio), \
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]21 .init = TEGRA_GPIO_INIT_##_init, \
22 }
23
24static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
Stephen Warren7f20bb22016-05-12 12:07:39 -0600[diff] [blame]25 /* port, pin, init_val */
26 GPIO_INIT(G, 0, IN),
27 GPIO_INIT(G, 1, IN),
28 GPIO_INIT(G, 2, IN),
29 GPIO_INIT(G, 3, IN),
30 GPIO_INIT(G, 4, IN),
31 GPIO_INIT(H, 2, OUT0),
32 GPIO_INIT(H, 4, IN),
33 GPIO_INIT(H, 7, IN),
34 GPIO_INIT(I, 0, OUT0),
35 GPIO_INIT(I, 1, IN),
36 GPIO_INIT(I, 6, IN),
37 GPIO_INIT(J, 0, IN),
38 GPIO_INIT(K, 1, OUT0),
39 GPIO_INIT(K, 2, IN),
40 GPIO_INIT(K, 4, OUT0),
41 GPIO_INIT(K, 6, OUT0),
42 GPIO_INIT(N, 7, IN),
43 GPIO_INIT(O, 1, IN),
44 GPIO_INIT(O, 4, IN),
45 GPIO_INIT(P, 2, OUT0),
46 GPIO_INIT(Q, 0, IN),
47 GPIO_INIT(Q, 3, IN),
48 GPIO_INIT(Q, 5, IN),
49 GPIO_INIT(R, 0, OUT0),
50 GPIO_INIT(R, 2, OUT0),
51 GPIO_INIT(R, 4, IN),
52 GPIO_INIT(R, 7, IN),
53 GPIO_INIT(S, 7, IN),
54 GPIO_INIT(T, 0, OUT0),
55 GPIO_INIT(T, 1, IN),
56 GPIO_INIT(U, 0, IN),
57 GPIO_INIT(U, 1, IN),
58 GPIO_INIT(U, 2, IN),
59 GPIO_INIT(U, 3, IN),
60 GPIO_INIT(U, 4, IN),
61 GPIO_INIT(U, 5, IN),
62 GPIO_INIT(U, 6, IN),
63 GPIO_INIT(V, 0, IN),
64 GPIO_INIT(V, 1, IN),
65 GPIO_INIT(X, 1, IN),
66 GPIO_INIT(X, 4, IN),
67 GPIO_INIT(X, 7, OUT0),
68 GPIO_INIT(BB, 3, OUT0),
69 GPIO_INIT(BB, 5, OUT0),
70 GPIO_INIT(BB, 6, OUT0),
71 GPIO_INIT(BB, 7, OUT0),
72 GPIO_INIT(CC, 1, IN),
73 GPIO_INIT(CC, 2, IN),
74 GPIO_INIT(EE, 2, OUT1),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]75};
76
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]77#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
78 { \
79 .pingrp = PMUX_PINGRP_##_pingrp, \
80 .func = PMUX_FUNC_##_mux, \
81 .pull = PMUX_PULL_##_pull, \
82 .tristate = PMUX_TRI_##_tri, \
83 .io = PMUX_PIN_##_io, \
84 .od = PMUX_PIN_OD_##_od, \
85 .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
86 .lock = PMUX_PIN_LOCK_DEFAULT, \
87 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
88 }
89
90static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
91 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]92 PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
93 PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
94 PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
95 PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
96 PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
97 PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
98 PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]99 PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]100 PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
101 PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]102 PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
103 PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
104 PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
105 PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]106 PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]107 PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]108 PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]109 PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
110 PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]111 PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
112 PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
113 PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
114 PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
115 PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
116 PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]117 PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
118 PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]119 PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]120 PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
121 PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]122 PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]123 PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
124 PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
125 PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
126 PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
127 PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]128 PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]129 PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
130 PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]131 PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]132 PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
133 PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
134 PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]135 PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]136 PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
137 PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
138 PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]139 PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
140 PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]141 PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]142 PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]143 PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
144 PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]145 PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]146 PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]147 PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]148 PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]149 PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
150 PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]151 PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]152 PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
153 PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
154 PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
155 PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
156 PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
157 PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
158 PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
159 PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
160 PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
161 PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
162 PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
163 PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
164 PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
165 PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]166 PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]167 PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]168 PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
169 PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
170 PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
171 PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
172 PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
173 PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
174 PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
175 PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
176 PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
177 PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
178 PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
179 PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]180 PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]181 PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]182 PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]183 PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
184 PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
185 PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
186 PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
187 PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
188 PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
189 PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
190 PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
191 PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
192 PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
193 PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
194 PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
195 PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]196 PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]197 PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]198 PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
199 PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
200 PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]201 PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
202 PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
203 PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
204 PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
205 PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
206 PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
207 PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
208 PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
209 PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
210 PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]211 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
212 PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
213 PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]214 PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
215 PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]216 PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
217 PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]218 PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
219 PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]220 PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]221 PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]222 PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]223 PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
224 PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
225 PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
226 PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]227 PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]228 PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]229 PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]230 PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
231 PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]232 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
233 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
234 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
235 PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
236 PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
237 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]238 PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
239 PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
240 PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
241 PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
242 PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
243 PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
244 PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
245 PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
246 PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
247 PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
248 PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
249 PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
250 PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]251 PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]252 PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenfa2a1232014-04-22 14:37:55 -0600[diff] [blame]253 PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
254 PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
255 PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]256 PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]257 PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
258 PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]259 PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]260 PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren25770112014-08-22 15:04:08 -0600[diff] [blame]261 PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]262 PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
263 PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warren25770112014-08-22 15:04:08 -0600[diff] [blame]264 PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]265 PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]266 PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]267 PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
268 PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
269 PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]270 PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
271 PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]272 PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
273 PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
274 PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]275 PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]276 PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
277 PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
278 PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren2516bef2015-02-18 13:27:04 -0700[diff] [blame]279 PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]280 PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
281};
282
283#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
284 { \
285 .drvgrp = PMUX_DRVGRP_##_drvgrp, \
286 .slwf = _slwf, \
287 .slwr = _slwr, \
288 .drvup = _drvup, \
289 .drvdn = _drvdn, \
290 .lpmd = PMUX_LPMD_##_lpmd, \
291 .schmt = PMUX_SCHMT_##_schmt, \
292 .hsm = PMUX_HSM_##_hsm, \
293 }
294
295static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
296};
297
Stephen Warren8e7c1be2016-04-21 16:03:37 -0600[diff] [blame]298#define MIPIPADCTRLCFG(_grp, _mux) \
299 { \
300 .grp = PMUX_MIPIPADCTRLGRP_##_grp, \
301 .func = PMUX_FUNC_##_mux, \
302 }
303
304static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
305 /* grp, mux */
306 MIPIPADCTRLCFG(DSI_B, DSI_B),
307};
308
Stephen Warrena844b012014-03-25 11:39:33 -0600[diff] [blame]309#endif /* PINMUX_CONFIG_JETSON_TK1_H */