Ashok Reddy Soma | 6f5480c | 2021-07-02 04:40:34 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Xilinx Multirate Ethernet MAC(MRMAC) driver |
| 4 | * |
| 5 | * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> |
| 6 | * Michal Simek <michal.simek@xilinx.com> |
| 7 | * |
| 8 | * Copyright (C) 2021 Xilinx, Inc. All rights reserved. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __XILINX_AXI_MRMAC_H |
| 12 | #define __XILINX_AXI_MRMAC_H |
| 13 | |
| 14 | #define MIN_PKT_SIZE 60 |
| 15 | |
| 16 | /* MRMAC needs atleast two buffer descriptors for Tx/Rx to work. |
| 17 | * Otherwise MRMAC will drop the packets. So, have atleast two Tx and |
| 18 | * two Rx bd's. |
| 19 | */ |
| 20 | #define TX_DESC 2 |
| 21 | #define RX_DESC 2 |
| 22 | |
| 23 | /* MRMAC platform data structure */ |
| 24 | struct axi_mrmac_plat { |
| 25 | struct eth_pdata eth_pdata; |
| 26 | struct mcdma_common_regs *mm2s_cmn; |
| 27 | u32 mrmac_rate; /* Hold the value from DT property "mrmac-rate" */ |
| 28 | }; |
| 29 | |
| 30 | /* MRMAC private driver structure */ |
| 31 | struct axi_mrmac_priv { |
| 32 | struct mrmac_regs *iobase; |
| 33 | struct mcdma_common_regs *mm2s_cmn; |
| 34 | struct mcdma_common_regs *s2mm_cmn; |
| 35 | struct mcdma_chan_reg *mcdma_tx; |
| 36 | struct mcdma_chan_reg *mcdma_rx; |
| 37 | struct mcdma_bd *tx_bd[TX_DESC]; |
| 38 | struct mcdma_bd *rx_bd[RX_DESC]; |
| 39 | u8 *txminframe; /* Pointer to hold min length Tx frame(60) */ |
| 40 | u32 mrmac_rate; /* Speed to configure(Read from DT 10G/25G..) */ |
| 41 | }; |
| 42 | |
| 43 | /* MRMAC Register Definitions */ |
| 44 | struct mrmac_regs { |
| 45 | u32 revision; /* 0x0: Revision Register */ |
| 46 | u32 reset; /* 0x4: Reset Register */ |
| 47 | u32 mode; /* 0x8: Mode */ |
| 48 | u32 tx_config; /* 0xc: Tx Configuration */ |
| 49 | u32 rx_config; /* 0x10: Rx Configuration */ |
| 50 | u32 reserved[6];/* 0x14-0x28: Reserved */ |
| 51 | u32 tick_reg; /* 0x2c: Tick Register */ |
| 52 | }; |
| 53 | |
| 54 | #define TX_BD_TOTAL_SIZE (TX_DESC * sizeof(struct mcdma_bd)) |
| 55 | #define RX_BD_TOTAL_SIZE (RX_DESC * sizeof(struct mcdma_bd)) |
| 56 | |
| 57 | #define RX_BUFF_TOTAL_SIZE (RX_DESC * PKTSIZE_ALIGN) |
| 58 | |
| 59 | /* Status Registers */ |
| 60 | #define MRMAC_TX_STS_OFFSET 0x740 |
| 61 | #define MRMAC_RX_STS_OFFSET 0x744 |
| 62 | #define MRMAC_TX_RT_STS_OFFSET 0x748 |
| 63 | #define MRMAC_RX_RT_STS_OFFSET 0x74c |
| 64 | #define MRMAC_STATRX_BLKLCK_OFFSET 0x754 |
| 65 | |
| 66 | /* Register bit masks */ |
| 67 | #define MRMAC_RX_SERDES_RST_MASK (BIT(3) | BIT(2) | BIT(1) | BIT(0)) |
| 68 | #define MRMAC_TX_SERDES_RST_MASK BIT(4) |
| 69 | #define MRMAC_RX_RST_MASK BIT(5) |
| 70 | #define MRMAC_TX_RST_MASK BIT(6) |
| 71 | #define MRMAC_RX_AXI_RST_MASK BIT(8) |
| 72 | #define MRMAC_TX_AXI_RST_MASK BIT(9) |
| 73 | #define MRMAC_STS_ALL_MASK 0xffffffff |
| 74 | |
| 75 | #define MRMAC_RX_EN_MASK BIT(0) |
| 76 | #define MRMAC_RX_DEL_FCS_MASK BIT(1) |
| 77 | |
| 78 | #define MRMAC_TX_EN_MASK BIT(0) |
| 79 | #define MRMAC_TX_INS_FCS_MASK BIT(1) |
| 80 | |
| 81 | #define MRMAC_RX_BLKLCK_MASK BIT(0) |
| 82 | |
| 83 | #define MRMAC_TICK_TRIGGER BIT(0) |
| 84 | |
| 85 | #define MRMAC_RESET_DELAY 1 /* Delay in msecs */ |
| 86 | #define MRMAC_BLKLCK_TIMEOUT 100 /* Block lock timeout in msecs */ |
| 87 | #define MRMAC_DMARST_TIMEOUT 500 /* MCDMA reset timeout in msecs */ |
| 88 | |
| 89 | #define XMCDMA_RX_OFFSET 0x500 |
| 90 | #define XMCDMA_CHAN_OFFSET 0x40 |
| 91 | |
| 92 | /* MCDMA Channel numbers are from 1-16 */ |
| 93 | #define XMCDMA_CHANNEL_1 BIT(0) |
| 94 | #define XMCDMA_CHANNEL_2 BIT(1) |
| 95 | |
| 96 | #define XMCDMA_CR_RUNSTOP BIT(0) |
| 97 | #define XMCDMA_CR_RESET BIT(2) |
| 98 | |
| 99 | #define XMCDMA_BD_CTRL_TXSOF_MASK BIT(31) /* First tx packet */ |
| 100 | #define XMCDMA_BD_CTRL_TXEOF_MASK BIT(30) /* Last tx packet */ |
| 101 | #define XMCDMA_BD_CTRL_ALL_MASK GENMASK(31, 30) /* All control bits */ |
| 102 | #define XMCDMA_BD_STS_ALL_MASK GENMASK(31, 28) /* All status bits */ |
| 103 | |
| 104 | /* MCDMA Mask registers */ |
| 105 | #define XMCDMA_CR_RUNSTOP_MASK BIT(0) /* Start/stop DMA channel */ |
| 106 | #define XMCDMA_CR_RESET_MASK BIT(2) /* Reset DMA engine */ |
| 107 | |
| 108 | #define XMCDMA_SR_HALTED_MASK BIT(0) |
| 109 | #define XMCDMA_SR_IDLE_MASK BIT(1) |
| 110 | |
| 111 | #define XMCDMA_CH_IDLE BIT(0) |
| 112 | |
| 113 | #define XMCDMA_BD_STS_COMPLETE BIT(31) /* Completed */ |
| 114 | #define XMCDMA_BD_STS_DEC_ERR BIT(20) /* Decode error */ |
| 115 | #define XMCDMA_BD_STS_SLV_ERR BIT(29) /* Slave error */ |
| 116 | #define XMCDMA_BD_STS_INT_ERR BIT(28) /* Internal err */ |
| 117 | #define XMCDMA_BD_STS_ALL_ERR GENMASK(30, 28) /* All errors */ |
| 118 | |
| 119 | #define XMCDMA_IRQ_ERRON_OTHERQ_MASK BIT(3) |
| 120 | #define XMCDMA_IRQ_PKTDROP_MASK BIT(4) |
| 121 | #define XMCDMA_IRQ_IOC_MASK BIT(5) |
| 122 | #define XMCDMA_IRQ_DELAY_MASK BIT(6) |
| 123 | #define XMCDMA_IRQ_ERR_MASK BIT(7) |
| 124 | #define XMCDMA_IRQ_ALL_MASK GENMASK(7, 5) |
| 125 | #define XMCDMA_PKTDROP_COALESCE_MASK GENMASK(15, 8) |
| 126 | #define XMCDMA_COALESCE_MASK GENMASK(23, 16) |
| 127 | #define XMCDMA_DELAY_MASK GENMASK(31, 24) |
| 128 | |
| 129 | #define MRMAC_CTL_DATA_RATE_MASK GENMASK(2, 0) |
| 130 | #define MRMAC_CTL_DATA_RATE_10G 0 |
| 131 | #define MRMAC_CTL_DATA_RATE_25G 1 |
| 132 | #define MRMAC_CTL_DATA_RATE_40G 2 |
| 133 | #define MRMAC_CTL_DATA_RATE_50G 3 |
| 134 | #define MRMAC_CTL_DATA_RATE_100G 4 |
| 135 | |
| 136 | #define MRMAC_CTL_AXIS_CFG_MASK GENMASK(11, 9) |
| 137 | #define MRMAC_CTL_AXIS_CFG_SHIFT 9 |
| 138 | #define MRMAC_CTL_AXIS_CFG_10G_IND 1 |
| 139 | #define MRMAC_CTL_AXIS_CFG_25G_IND 1 |
| 140 | |
| 141 | #define MRMAC_CTL_SERDES_WIDTH_MASK GENMASK(6, 4) |
| 142 | #define MRMAC_CTL_SERDES_WIDTH_SHIFT 4 |
| 143 | #define MRMAC_CTL_SERDES_WIDTH_10G 4 |
| 144 | #define MRMAC_CTL_SERDES_WIDTH_25G 6 |
| 145 | |
| 146 | #define MRMAC_CTL_RATE_CFG_MASK (MRMAC_CTL_DATA_RATE_MASK | \ |
| 147 | MRMAC_CTL_AXIS_CFG_MASK | \ |
| 148 | MRMAC_CTL_SERDES_WIDTH_MASK) |
| 149 | |
| 150 | #define MRMAC_CTL_PM_TICK_MASK BIT(30) |
| 151 | #define MRMAC_TICK_TRIGGER BIT(0) |
| 152 | |
| 153 | #define XMCDMA_BD_STS_ACTUAL_LEN_MASK 0x007fffff /* Actual length */ |
| 154 | |
| 155 | /* MCDMA common offsets */ |
| 156 | struct mcdma_common_regs { |
| 157 | u32 control; /* Common control */ |
| 158 | u32 status; /* Common status */ |
| 159 | u32 chen; /* Channel enable/disable */ |
| 160 | u32 chser; /* Channel in progress */ |
| 161 | u32 err; /* Error */ |
| 162 | u32 ch_schd_type; /* Channel Q scheduler type */ |
| 163 | u32 wrr_reg1; /* Weight of each channel (ch1-8) */ |
| 164 | u32 wrr_reg2; /* Weight of each channel (ch9-16) */ |
| 165 | u32 ch_serviced; /* Channels completed */ |
| 166 | u32 arcache_aruser; /* ARCACHE and ARUSER values for AXI4 read */ |
| 167 | u32 intr_status; /* Interrupt monitor */ |
| 168 | u32 reserved[5]; |
| 169 | }; |
| 170 | |
| 171 | /* MCDMA per-channel registers */ |
| 172 | struct mcdma_chan_reg { |
| 173 | u32 control; /* Control */ |
| 174 | u32 status; /* Status */ |
| 175 | u32 current; /* Current descriptor */ |
| 176 | u32 current_hi; /* Current descriptor high 32bit */ |
| 177 | u32 tail; /* Tail descriptor */ |
| 178 | u32 tail_hi; /* Tail descriptor high 32bit */ |
| 179 | u32 pktcnt; /* Packet processed count */ |
| 180 | }; |
| 181 | |
| 182 | /* MCDMA buffer descriptors */ |
| 183 | struct mcdma_bd { |
| 184 | u32 next_desc; /* Next descriptor pointer */ |
| 185 | u32 next_desc_msb; |
| 186 | u32 buf_addr; /* Buffer address */ |
| 187 | u32 buf_addr_msb; |
| 188 | u32 reserved1; |
| 189 | u32 cntrl; /* Control */ |
| 190 | u32 status; /* Status */ |
| 191 | u32 sband_stats; |
| 192 | u32 app0; |
| 193 | u32 app1; /* Tx start << 16 | insert */ |
| 194 | u32 app2; /* Tx csum seed */ |
| 195 | u32 app3; |
| 196 | u32 app4; |
| 197 | u32 sw_id_offset; |
| 198 | u32 reserved2; |
| 199 | u32 reserved3; |
| 200 | u32 reserved4[16]; |
| 201 | }; |
| 202 | |
| 203 | #endif /* __XILINX_AXI_MRMAC_H */ |