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git01.mediatek.com / filogic / uboot / fab0bd397e9ae8a73ac5e7e7161f52069775e0a9 / . / arch / arm / dts / rk3399-puma-haikou-u-boot.dtsi
blob: d1912a2ef6a966cd4d1e0053649c58ce6580af57 [file] [log] [blame]
Peter Robinson606050d2020-01-20 09:18:18 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2
3#include "rk3399-u-boot.dtsi"
Heiko Stuebnere2a55862020-06-05 12:06:40 +0200[diff] [blame]4
5#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1333
6#include "rk3399-sdram-ddr3-1333.dtsi"
7#endif
8#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1600
9#include "rk3399-sdram-ddr3-1600.dtsi"
10#endif
11#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1866
12#include "rk3399-sdram-ddr3-1866.dtsi"
13#endif
14
Peter Robinson606050d2020-01-20 09:18:18 +0000[diff] [blame]15/ {
Heiko Stuebnerc71acd12020-06-05 12:06:38 +0200[diff] [blame]16 config {
Quentin Schulz0088ca42022-09-15 11:14:29 +0200[diff] [blame]17 u-boot,spl-payload-offset = <0x80000>; /* @ 512KB */
Quentin Schulz56173452022-10-25 12:58:02 +0200[diff] [blame]18 u-boot,mmc-env-offset = <0x5000>; /* @ 20KB */
Heiko Stuebnerc71acd12020-06-05 12:06:38 +0200[diff] [blame]19 u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
20 u-boot,boot-led = "module_led";
21 sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
22 };
Peter Robinson606050d2020-01-20 09:18:18 +0000[diff] [blame]23
Heiko Stuebnerc71acd12020-06-05 12:06:38 +0200[diff] [blame]24 chosen {
25 stdout-path = "serial0:115200n8";
26 u-boot,spl-boot-order = \
Jagan Teki5cc21182020-04-28 15:30:17 +0530[diff] [blame]27 "same-as-spl", &norflash, &sdhci, &sdmmc;
Heiko Stuebnerc71acd12020-06-05 12:06:38 +0200[diff] [blame]28 };
Peter Robinson606050d2020-01-20 09:18:18 +0000[diff] [blame]29
Heiko Stuebnerc71acd12020-06-05 12:06:38 +0200[diff] [blame]30 aliases {
Hugh Cole-Baker2d338232020-11-22 13:03:46 +0000[diff] [blame]31 spi5 = &spi5;
Heiko Stuebnerc71acd12020-06-05 12:06:38 +0200[diff] [blame]32 };
Peter Robinson606050d2020-01-20 09:18:18 +0000[diff] [blame]33
Christoph Muellnerfc283612021-02-19 01:29:48 +0100[diff] [blame]34 vdd_log: vdd-log {
35 compatible = "pwm-regulator";
36 pwms = <&pwm2 0 25000 1>;
37 regulator-name = "vdd_log";
38 regulator-always-on;
39 regulator-boot-on;
40 regulator-min-microvolt = <800000>;
41 regulator-max-microvolt = <1400000>;
42 regulator-init-microvolt = <950000>;
43 vin-supply = <&vcc5v0_sys>;
44 };
Peter Robinson606050d2020-01-20 09:18:18 +0000[diff] [blame]45};
Jagan Teki435970a2020-04-28 15:30:14 +0530[diff] [blame]46
Quentin Schulzd7bd8152022-09-15 11:14:30 +0200[diff] [blame]47&binman {
48 simple-bin {
Simon Glass4de36172023-01-07 14:07:18 -0700[diff] [blame]49 fit {
Quentin Schulzd7bd8152022-09-15 11:14:30 +0200[diff] [blame]50 offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
51 };
52 };
Quentin Schulz744fc432022-09-15 11:14:32 +0200[diff] [blame]53
54#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
55 simple-bin-spi {
Simon Glass4de36172023-01-07 14:07:18 -0700[diff] [blame]56 fit {
Quentin Schulz744fc432022-09-15 11:14:32 +0200[diff] [blame]57 /* same as u-boot,spl-payload-offset */
58 offset = <0x80000>;
59 };
60 };
61#endif
Quentin Schulzd7bd8152022-09-15 11:14:30 +0200[diff] [blame]62};
63
Jagan Teki435970a2020-04-28 15:30:14 +0530[diff] [blame]64&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-all;
Jagan Teki435970a2020-04-28 15:30:14 +0530[diff] [blame]66};
67
68&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-all;
Quentin Schulza0fb0bd2022-09-15 11:14:22 +0200[diff] [blame]70
71 /*
72 * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
73 * eMMC and SPI flash powered-down initially (in fact it keeps the
74 * reset signal asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable
75 * eMMC and SPI after the SPL has been booted from SD Card.
76 */
77 bios_disable_override {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-all;
Quentin Schulza0fb0bd2022-09-15 11:14:22 +0200[diff] [blame]79 gpios = <RK_PD5 GPIO_ACTIVE_LOW>;
80 output-high;
81 line-name = "bios_disable_override";
82 gpio-hog;
83 };
Jagan Teki435970a2020-04-28 15:30:14 +0530[diff] [blame]84};
85
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]86&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-all;
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]88};
89
Jagan Teki5cc21182020-04-28 15:30:17 +0530[diff] [blame]90&norflash {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-all;
Jagan Teki435970a2020-04-28 15:30:14 +0530[diff] [blame]92};
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]93
94&pcfg_pull_none {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-all;
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]96};
97
98&pcfg_pull_up {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-all;
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]100};
101
102&sdmmc_bus4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-all;
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]104};
105
106&sdmmc_clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-all;
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]108};
109
110&sdmmc_cmd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-all;
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]112};
Jonas Karlman3a926122024-04-30 15:30:22 +0000[diff] [blame]113
114&uart0 {
115 bootph-all;
Jonas Karlmanfab0bd32024-04-30 15:30:23 +0000[diff] [blame^]116 clock-frequency = <24000000>;
117};
118
119&uart0_cts {
120 bootph-pre-sram;
121 bootph-pre-ram;
122};
123
124&uart0_rts {
125 bootph-pre-sram;
126 bootph-pre-ram;
127};
128
129&uart0_xfer {
130 bootph-pre-sram;
131 bootph-pre-ram;
Jonas Karlman3a926122024-04-30 15:30:22 +0000[diff] [blame]132};