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Peng Fanf664c142015-08-13 10:55:34 +08001/*
2 * (C) Copyright 2009
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _SYS_PROTO_H_
9#define _SYS_PROTO_H_
10
11#include <asm/imx-common/regs-common.h>
12#include <common.h>
13#include "../arch-imx/cpu.h"
14
15#define soc_rev() (get_cpu_rev() & 0xFF)
16#define is_soc_rev(rev) (soc_rev() == rev)
17
18/* returns MXC_CPU_ value */
19#define cpu_type(rev) (((rev) >> 12) & 0xff)
Adrian Alonso1eec27c2015-09-02 13:54:12 -050020#define soc_type(rev) (((rev) >> 12) & 0xf0)
Peng Fanf664c142015-08-13 10:55:34 +080021/* both macros return/take MXC_CPU_ constants */
22#define get_cpu_type() (cpu_type(get_cpu_rev()))
Adrian Alonso1eec27c2015-09-02 13:54:12 -050023#define get_soc_type() (soc_type(get_cpu_rev()))
Peng Fanf664c142015-08-13 10:55:34 +080024#define is_cpu_type(cpu) (get_cpu_type() == cpu)
Adrian Alonso1eec27c2015-09-02 13:54:12 -050025#define is_soc_type(soc) (get_soc_type() == soc)
Peng Fanf664c142015-08-13 10:55:34 +080026
27#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
28
29u32 get_nr_cpus(void);
30u32 get_cpu_rev(void);
31u32 get_cpu_speed_grade_hz(void);
32u32 get_cpu_temp_grade(int *minc, int *maxc);
33const char *get_imx_type(u32 imxtype);
34u32 imx_ddr_size(void);
35void sdelay(unsigned long);
36void set_chipselect_size(int const);
37
Adrian Alonsoee7c4ca2015-09-02 13:54:15 -050038void init_aips(void);
39void init_src(void);
Adrian Alonso51d70f72015-09-02 13:54:21 -050040void imx_set_wdog_powerdown(bool enable);
Adrian Alonsoee7c4ca2015-09-02 13:54:15 -050041
Peng Fanf664c142015-08-13 10:55:34 +080042/*
43 * Initializes on-chip ethernet controllers.
44 * to override, implement board_eth_init()
45 */
46int fecmxc_initialize(bd_t *bis);
47u32 get_ahb_clk(void);
48u32 get_periph_clk(void);
49
Peng Fan5f8dbf52015-10-29 15:54:49 +080050void lcdif_power_down(void);
51
Peng Fanf664c142015-08-13 10:55:34 +080052int mxs_reset_block(struct mxs_register_32 *reg);
53int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
54int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
55#endif