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Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09001/*
2 * UniPhier UMC (Universal Memory Controller) registers
3 *
4 * Copyright (C) 2011-2014 Panasonic Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef ARCH_UMC_REGS_H
10#define ARCH_UMC_REGS_H
11
12#define UMC_BASE 0x5b800000
13
14/* SSIF registers */
15#define UMC_SSIF_BASE UMC_BASE
16
17#define UMC_CPURST 0x00000700
18#define UMC_IDSRST 0x0000070C
19#define UMC_IXMRST 0x00000714
20#define UMC_HDMRST 0x00000718
21#define UMC_MDMRST 0x0000071C
22#define UMC_HDDRST 0x00000720
23#define UMC_MDDRST 0x00000724
24#define UMC_SIORST 0x00000728
25#define UMC_GIORST 0x0000072C
26#define UMC_HD2RST 0x00000734
27#define UMC_VIORST 0x0000073C
28#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
29#define UMC_DVCRST 0x00000748 /* Pro4 */
30#define UMC_RGLRST 0x00000750
31#define UMC_VPERST 0x00000758
32#define UMC_AIORST 0x00000764
33#define UMC_DMDRST 0x00000770
34
35#define UMC_HDMCHSEL 0x00000898
36#define UMC_MDMCHSEL 0x0000089C
37#define UMC_DVCCHSEL 0x000008C8
38#define UMC_DMDCHSEL 0x000008F0
39
40#define UMC_CLKEN_SSIF_FETCH 0x0000C060
41#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
42#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
43#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
44#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
45#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
46#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
47#define UMC_CLKEN_SSIF_WC 0x0000C07C
48#define UMC_CLKEN_SSIF_RC 0x0000C080
49#define UMC_CLKEN_SSIF_DST 0x0000C084
50
51/* CA registers */
52#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
53
54/* DRAM controller registers */
55#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
56
57#define UMC_CMDCTLA 0x00000000
58#define UMC_CMDCTLB 0x00000004
59#define UMC_INITCTLA 0x00000008
60#define UMC_INITCTLB 0x0000000C
61#define UMC_INITCTLC 0x00000010
62#define UMC_INITSET 0x00000014
63#define UMC_INITSTAT 0x00000018
64#define UMC_DRMMR0 0x0000001C
65#define UMC_DRMMR1 0x00000020
66#define UMC_DRMMR2 0x00000024
67#define UMC_DRMMR3 0x00000028
68#define UMC_SPCCTLA 0x00000030
69#define UMC_SPCCTLB 0x00000034
70#define UMC_SPCSETA 0x00000038
71#define UMC_SPCSETB 0x0000003C
72#define UMC_SPCSETC 0x00000040
73#define UMC_SPCSETD 0x00000044
74#define UMC_SPCSTATA 0x00000050
75#define UMC_SPCSTATB 0x00000054
76#define UMC_SPCSTATC 0x00000058
77#define UMC_ACSSETA 0x00000060
78#define UMC_FLOWCTLA 0x00000400
79#define UMC_FLOWCTLB 0x00000404
80#define UMC_FLOWCTLC 0x00000408
81#define UMC_FLOWCTLG 0x00000508
82#define UMC_RDATACTL_D0 0x00000600
83#define UMC_WDATACTL_D0 0x00000604
84#define UMC_RDATACTL_D1 0x00000608
85#define UMC_WDATACTL_D1 0x0000060C
86#define UMC_DATASET 0x00000610
87#define UMC_DCCGCTL 0x00000720
88#define UMC_DICGCTLA 0x00000724
89#define UMC_DICGCTLB 0x00000728
90#define UMC_DIOCTLA 0x00000C00
91#define UMC_DFICUPDCTLA 0x00000C20
92
93#ifndef __ASSEMBLY__
94
95#include <linux/types.h>
96
97static inline void umc_polling(u32 address, u32 expval, u32 mask)
98{
99 u32 nmask = ~mask;
100 u32 data;
101 do {
102 data = readl(address) & nmask;
103 } while (data != expval);
104}
105
106static inline void umc_dram_init_start(void __iomem *dramcont)
107{
108 writel(0x00000002, dramcont + UMC_INITSET);
109}
110
111static inline void umc_dram_init_poll(void __iomem *dramcont)
112{
113 while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
114 ;
115}
116
117#endif
118
119#endif