Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 1 | /* |
| 2 | * UniPhier SG (SoC Glue) block registers |
| 3 | * |
Masahiro Yamada | 663a23f | 2015-05-29 17:30:00 +0900 | [diff] [blame] | 4 | * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef ARCH_SG_REGS_H |
| 10 | #define ARCH_SG_REGS_H |
| 11 | |
| 12 | /* Base Address */ |
| 13 | #define SG_CTRL_BASE 0x5f800000 |
| 14 | #define SG_DBG_BASE 0x5f900000 |
| 15 | |
| 16 | /* Revision */ |
| 17 | #define SG_REVISION (SG_CTRL_BASE | 0x0000) |
| 18 | #define SG_REVISION_TYPE_SHIFT 16 |
| 19 | #define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT) |
| 20 | #define SG_REVISION_MODEL_SHIFT 8 |
| 21 | #define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT) |
| 22 | #define SG_REVISION_REV_SHIFT 0 |
| 23 | #define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT) |
| 24 | |
| 25 | /* Memory Configuration */ |
| 26 | #define SG_MEMCONF (SG_CTRL_BASE | 0x0400) |
| 27 | |
Masahiro Yamada | 0d513f9 | 2015-01-21 15:27:47 +0900 | [diff] [blame] | 28 | #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) |
| 29 | #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) |
| 30 | #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) |
| 31 | #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) |
| 32 | #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 33 | #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) |
| 34 | #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) |
| 35 | |
Masahiro Yamada | 0d513f9 | 2015-01-21 15:27:47 +0900 | [diff] [blame] | 36 | #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) |
| 37 | #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) |
| 38 | #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) |
| 39 | #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) |
| 40 | #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 41 | #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) |
| 42 | #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) |
| 43 | |
Masahiro Yamada | c3158ea | 2015-01-21 15:27:48 +0900 | [diff] [blame] | 44 | #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) |
| 45 | #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) |
| 46 | #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) |
| 47 | #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) |
| 48 | #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) |
| 49 | #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) |
| 50 | |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 51 | #define SG_MEMCONF_SPARSEMEM (0x1 << 4) |
| 52 | |
| 53 | /* Pin Control */ |
| 54 | #define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) |
| 55 | |
| 56 | #if defined(CONFIG_MACH_PH1_PRO4) |
| 57 | # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8) |
Masahiro Yamada | fa71441 | 2015-07-21 14:04:22 +0900 | [diff] [blame^] | 58 | #elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ |
| 59 | defined(CONFIG_MACH_PH1_SLD8) |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 60 | # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4) |
| 61 | #endif |
| 62 | |
Masahiro Yamada | fa71441 | 2015-07-21 14:04:22 +0900 | [diff] [blame^] | 63 | #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4) |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 64 | #define SG_PINSELBITS 4 |
| 65 | #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) |
| 66 | #define SG_PINSELBITS 8 |
| 67 | #endif |
| 68 | |
| 69 | #define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32)) |
| 70 | #define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \ |
| 71 | ((n) * (SG_PINSELBITS) % 32))) |
| 72 | #define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32)) |
| 73 | |
| 74 | /* Only for PH1-Pro4 */ |
| 75 | #define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) |
| 76 | |
| 77 | /* Input Enable */ |
| 78 | #define SG_IECTRL (SG_CTRL_BASE | 0x1d00) |
| 79 | |
| 80 | /* Pin Monitor */ |
| 81 | #define SG_PINMON0 (SG_DBG_BASE | 0x0100) |
| 82 | |
| 83 | #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) |
| 84 | #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) |
| 85 | #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19) |
| 86 | #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19) |
| 87 | |
| 88 | #define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16) |
| 89 | #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16) |
| 90 | #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16) |
| 91 | #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16) |
| 92 | #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16) |
| 93 | |
| 94 | #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16) |
| 95 | #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16) |
| 96 | #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) |
| 97 | #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) |
| 98 | |
Masahiro Yamada | 762b453 | 2014-11-07 21:08:52 +0900 | [diff] [blame] | 99 | #ifdef __ASSEMBLY__ |
| 100 | |
| 101 | .macro set_pinsel, n, value, ra, rd |
| 102 | ldr \ra, =SG_PINSEL_ADDR(\n) |
| 103 | ldr \rd, [\ra] |
| 104 | and \rd, \rd, #SG_PINSEL_MASK(\n) |
| 105 | orr \rd, \rd, #SG_PINSEL_MODE(\n, \value) |
| 106 | str \rd, [\ra] |
| 107 | .endm |
| 108 | |
| 109 | #else |
| 110 | |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 111 | #include <linux/types.h> |
Masahiro Yamada | 663a23f | 2015-05-29 17:30:00 +0900 | [diff] [blame] | 112 | #include <linux/io.h> |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 113 | |
| 114 | static inline void sg_set_pinsel(int n, int value) |
| 115 | { |
| 116 | writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n)) |
| 117 | | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n)); |
| 118 | } |
| 119 | |
Masahiro Yamada | bb2ff9d | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 120 | #endif /* __ASSEMBLY__ */ |
| 121 | |
| 122 | #endif /* ARCH_SG_REGS_H */ |