blob: af2bf804115769e3d5deabf00b0855eb6b4c0797 [file] [log] [blame]
Dirk Behme7b84a7b2009-01-28 21:39:58 +01001/*
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -05002 * (C) Copyright 2008-2010
3 * GraÅžvydas Ignotas <notasas@gmail.com>
Dirk Behme7b84a7b2009-01-28 21:39:58 +01004 *
5 * Configuration settings for the OMAP3 Pandora.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
Dirk Behme7b84a7b2009-01-28 21:39:58 +010025
26/*
27 * High Level Configuration Options
28 */
Dirk Behme7b84a7b2009-01-28 21:39:58 +010029#define CONFIG_OMAP 1 /* in a TI OMAP core */
30#define CONFIG_OMAP34XX 1 /* which is a 34XX */
31#define CONFIG_OMAP3430 1 /* which is in a 3430 */
32#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
33
Vaibhav Hiremath558d23d2010-06-07 15:20:34 -040034#define CONFIG_SDRC /* The chip has SDRC controller */
35
Dirk Behme7b84a7b2009-01-28 21:39:58 +010036#include <asm/arch/cpu.h> /* get chip and board defs */
37#include <asm/arch/omap3.h>
38
Sanjeev Premie32ef2e2009-04-27 21:27:27 +053039/*
40 * Display CPU and Board information
41 */
42#define CONFIG_DISPLAY_CPUINFO 1
43#define CONFIG_DISPLAY_BOARDINFO 1
44
Dirk Behme7b84a7b2009-01-28 21:39:58 +010045/* Clock Defines */
46#define V_OSCK 26000000 /* Clock output from T2 */
47#define V_SCLK (V_OSCK >> 1)
48
49#undef CONFIG_USE_IRQ /* no support for IRQs */
50#define CONFIG_MISC_INIT_R
51
52#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
53#define CONFIG_SETUP_MEMORY_TAGS 1
54#define CONFIG_INITRD_TAG 1
55#define CONFIG_REVISION_TAG 1
56
Grant Likely100b8492011-03-28 09:59:07 +000057#define CONFIG_OF_LIBFDT 1
58
Dirk Behme7b84a7b2009-01-28 21:39:58 +010059/*
60 * Size of malloc() pool
61 */
Sandeep Paulraj6a87b3f2009-09-09 11:50:40 -040062#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -050063#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
Dirk Behme7b84a7b2009-01-28 21:39:58 +010064
65/*
66 * Hardware drivers
67 */
68
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -050069#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
70#define CONFIG_SYS_DEVICE_NULLDEV 1
71
72/* USB */
73#define CONFIG_MUSB_UDC 1
74#define CONFIG_USB_OMAP3 1
75#define CONFIG_TWL4030_USB 1
76
77/* USB device configuration */
78#define CONFIG_USB_DEVICE 1
79#define CONFIG_USB_TTY 1
80
Dirk Behme7b84a7b2009-01-28 21:39:58 +010081/*
82 * NS16550 Configuration
83 */
84#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
85
86#define CONFIG_SYS_NS16550
87#define CONFIG_SYS_NS16550_SERIAL
88#define CONFIG_SYS_NS16550_REG_SIZE (-4)
89#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
90
91/*
92 * select serial console configuration
93 */
94#define CONFIG_CONS_INDEX 3
95#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
96#define CONFIG_SERIAL3 3
97
98/* allow to overwrite serial and ethaddr */
99#define CONFIG_ENV_OVERWRITE
100#define CONFIG_BAUDRATE 115200
101#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
102 115200}
Tom Rini83922512011-09-03 21:51:25 -0400103#define CONFIG_GENERIC_MMC 1
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100104#define CONFIG_MMC 1
Tom Rini83922512011-09-03 21:51:25 -0400105#define CONFIG_OMAP_HSMMC 1
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100106#define CONFIG_DOS_PARTITION 1
107
Nishanth Menon076501b2009-11-07 10:51:24 -0500108/* DDR - I use Micron DDR */
109#define CONFIG_OMAP3_MICRON_DDR 1
110
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100111/* commands to include */
112#include <config_cmd_default.h>
113
114#define CONFIG_CMD_EXT2 /* EXT2 Support */
115#define CONFIG_CMD_FAT /* FAT support */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100116
117#define CONFIG_CMD_I2C /* I2C serial bus support */
118#define CONFIG_CMD_MMC /* MMC support */
119#define CONFIG_CMD_NAND /* NAND support */
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -0500120#define CONFIG_CMD_CACHE /* Cache control */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100121
122#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
123#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
124#undef CONFIG_CMD_IMI /* iminfo */
125#undef CONFIG_CMD_IMLS /* List all found images */
126#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
127#undef CONFIG_CMD_NFS /* NFS support */
128
129#define CONFIG_SYS_NO_FLASH
Tom Rixd77b6812009-09-29 10:19:49 -0400130#define CONFIG_HARD_I2C 1
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100131#define CONFIG_SYS_I2C_SPEED 100000
132#define CONFIG_SYS_I2C_SLAVE 1
133#define CONFIG_SYS_I2C_BUS 0
134#define CONFIG_SYS_I2C_BUS_SELECT 1
135#define CONFIG_DRIVER_OMAP34XX_I2C 1
136
137/*
Tom Rix0f2a8042009-06-28 12:52:30 -0500138 * TWL4030
139 */
140#define CONFIG_TWL4030_POWER 1
141#define CONFIG_TWL4030_LED 1
142
143/*
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100144 * Board NAND Info.
145 */
146#define CONFIG_NAND_OMAP_GPMC
147#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
148 /* to access nand */
149#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
150 /* to access nand */
151 /* at CS0 */
152#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
153
154#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
155 /* devices */
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -0500156
157#ifdef CONFIG_CMD_NAND
158#define CONFIG_CMD_MTDPARTS
159#define CONFIG_MTD_PARTITIONS
160#define CONFIG_MTD_DEVICE
161#define CONFIG_CMD_UBI
162#define CONFIG_CMD_UBIFS
163#define CONFIG_RBTREE
164#define CONFIG_LZO
165
166#define MTDIDS_DEFAULT "nand0=nand"
167#define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader),"\
168 "1920k(uboot),128k(uboot-env),"\
169 "10m(boot),-(rootfs)"
170#else
171#define MTDPARTS_DEFAULT
172#endif
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100173
174/* Environment information */
175#define CONFIG_BOOTDELAY 1
176
177#define CONFIG_EXTRA_ENV_SETTINGS \
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -0500178 "usbtty=cdc_acm\0" \
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100179 "loadaddr=0x82000000\0" \
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -0500180 "bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
181 "rw rootflags=bulk_read console=ttyS0,115200n8 " \
182 "vram=6272K omapfb.vram=0:3000K\0" \
183 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100184
185#define CONFIG_BOOTCOMMAND \
Tom Rini83922512011-09-03 21:51:25 -0400186 "if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr || " \
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -0500187 "ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
188 "source ${loadaddr}; " \
189 "fi; " \
190 "ubi part boot && ubifsmount boot && ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100191
192#define CONFIG_AUTO_COMPLETE 1
193/*
194 * Miscellaneous configurable options
195 */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100196#define CONFIG_SYS_LONGHELP /* undef to save memory */
197#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
198#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Robert P. J. Day23f5a2d2009-12-12 12:10:33 -0500199#define CONFIG_SYS_PROMPT "Pandora # "
Vaibhav Hiremathe1832902011-09-03 21:24:19 -0400200#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100201/* Print Buffer Size */
202#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
203 sizeof(CONFIG_SYS_PROMPT) + 16)
204#define CONFIG_SYS_MAXARGS 16 /* max number of command */
205 /* args */
206/* Boot Argument Buffer Size */
207#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
208/* memtest works on */
209#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
210#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
211 0x01F00000) /* 31MB */
212
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100213#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
214 /* address */
215
216/*
Manikandan Pillaie8b16962009-04-21 17:29:05 +0200217 * OMAP3 has 12 GP timers, they can be driven by the system clock
218 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
219 * This rate is divided by a local divisor.
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100220 */
Manikandan Pillaie8b16962009-04-21 17:29:05 +0200221#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
222#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
223#define CONFIG_SYS_HZ 1000
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100224
225/*-----------------------------------------------------------------------
226 * Stack sizes
227 *
228 * The stack sizes are set up in start.S using the settings below
229 */
Sandeep Paulraj6a87b3f2009-09-09 11:50:40 -0400230#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100231#ifdef CONFIG_USE_IRQ
Sandeep Paulraj6a87b3f2009-09-09 11:50:40 -0400232#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
233#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100234#endif
235
236/*-----------------------------------------------------------------------
237 * Physical Memory Map
238 */
239#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
240#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sandeep Paulraj6a87b3f2009-09-09 11:50:40 -0400241#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100242#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
243
244/* SDRAM Bank Allocation method */
245#define SDRC_R_B_C 1
246
Grazvydas Ignotasa3e22f62010-11-19 11:25:31 -0500247#define CONFIG_SYS_TEXT_BASE 0x80008000
248#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
249#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
250#define CONFIG_SYS_INIT_RAM_SIZE 0x800
251#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
252 CONFIG_SYS_INIT_RAM_SIZE - \
253 GENERATED_GBL_DATA_SIZE)
254
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100255/*-----------------------------------------------------------------------
256 * FLASH and environment organization
257 */
258
259/* **** PISMO SUPPORT *** */
260
261/* Configure the PISMO */
262#define PISMO1_NAND_SIZE GPMC_SIZE_128M
263#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
264
Sandeep Paulraj6a87b3f2009-09-09 11:50:40 -0400265#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100266
Luca Ceresoli9783a2c2011-04-20 11:02:05 -0400267#if defined(CONFIG_CMD_NAND)
268#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
269#endif
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100270
271/* Monitor at start of flash */
272#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100273
274#define CONFIG_ENV_IS_IN_NAND 1
Grazvydas Ignotas9f4de642010-11-19 11:25:36 -0500275#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100276
Luca Ceresoli9783a2c2011-04-20 11:02:05 -0400277#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
278#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100279#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
280
Aneesh Vfa5c07a2011-11-21 23:38:59 +0000281#define CONFIG_SYS_CACHELINE_SIZE 64
282
Dirk Behme7b84a7b2009-01-28 21:39:58 +0100283#endif /* __CONFIG_H */