blob: 42a8131bd50b2898d84be5972d1645b3cd08f856 [file] [log] [blame]
Bin Menge1c49352015-07-30 03:49:17 -07001/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/x86-gpio.h>
Bin Meng947391c2015-07-30 03:49:18 -070010#include <dt-bindings/interrupt-router/intel-irq.h>
Bin Menge1c49352015-07-30 03:49:17 -070011
12/include/ "skeleton.dtsi"
Simon Glass3356cad2015-11-11 10:05:43 -070013/include/ "keyboard.dtsi"
Bin Menge1c49352015-07-30 03:49:17 -070014/include/ "serial.dtsi"
15/include/ "rtc.dtsi"
Bin Meng38de0202015-11-13 00:11:22 -080016/include/ "tsc_timer.dtsi"
Bin Menga4470172016-10-09 04:14:18 -070017/include/ "coreboot_fb.dtsi"
Bin Menge1c49352015-07-30 03:49:17 -070018
19/ {
20 model = "Intel Bayley Bay";
21 compatible = "intel,bayleybay", "intel,baytrail";
22
23 aliases {
24 serial0 = &serial;
Bin Meng4f8d4e92016-01-27 00:56:34 -080025 spi0 = &spi;
Bin Menge1c49352015-07-30 03:49:17 -070026 };
27
28 config {
29 silent_console = <0>;
30 };
31
32 chosen {
33 stdout-path = "/serial";
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 device_type = "cpu";
42 compatible = "intel,baytrail-cpu";
43 reg = <0>;
44 intel,apic-id = <0>;
45 };
46
47 cpu@1 {
48 device_type = "cpu";
49 compatible = "intel,baytrail-cpu";
50 reg = <1>;
51 intel,apic-id = <2>;
52 };
53
54 cpu@2 {
55 device_type = "cpu";
56 compatible = "intel,baytrail-cpu";
57 reg = <2>;
58 intel,apic-id = <4>;
59 };
60
61 cpu@3 {
62 device_type = "cpu";
63 compatible = "intel,baytrail-cpu";
64 reg = <3>;
65 intel,apic-id = <6>;
66 };
67 };
68
Bin Mengde6d1982016-06-08 05:07:33 -070069 pch_pinctrl {
70 compatible = "intel,x86-pinctrl";
71 reg = <0 0>;
Bin Menge4d977f2016-06-08 05:07:35 -070072
73 /*
74 * As of today, the latest version FSP (gold4) for BayTrail
75 * misses the PAD configuration of the SD controller's Card
76 * Detect signal. The default PAD value for the CD pin sets
77 * the pin to work in GPIO mode, which causes card detect
78 * status cannot be reflected by the Present State register
79 * in the SD controller (bit 16 & bit 18 are always zero).
80 *
81 * Configure this pin to function 1 (SD controller).
82 */
83 sdmmc3_cd@0 {
84 pad-offset = <0x3a0>;
85 mode-func = <1>;
86 };
Bin Mengde6d1982016-06-08 05:07:33 -070087 };
88
Bin Menge1c49352015-07-30 03:49:17 -070089 pci {
90 compatible = "pci-x86";
91 #address-cells = <3>;
92 #size-cells = <2>;
93 u-boot,dm-pre-reloc;
94 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
95 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
96 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
Bin Meng947391c2015-07-30 03:49:18 -070097
Simon Glass32761632016-01-18 20:19:21 -070098 pch@1f,0 {
Bin Meng947391c2015-07-30 03:49:18 -070099 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700100 compatible = "intel,pch9";
Bin Meng6e916cc2016-02-01 01:40:47 -0800101 #address-cells = <1>;
102 #size-cells = <1>;
Bin Meng947391c2015-07-30 03:49:18 -0700103
Simon Glass32761632016-01-18 20:19:21 -0700104 irq-router {
105 compatible = "intel,irq-router";
106 intel,pirq-config = "ibase";
107 intel,ibase-offset = <0x50>;
Bin Meng0651f622016-05-07 07:46:15 -0700108 intel,actl-addr = <0>;
Simon Glass32761632016-01-18 20:19:21 -0700109 intel,pirq-link = <8 8>;
110 intel,pirq-mask = <0xdee0>;
111 intel,pirq-routing = <
112 /* BayTrail PCI devices */
113 PCI_BDF(0, 2, 0) INTA PIRQA
114 PCI_BDF(0, 3, 0) INTA PIRQA
115 PCI_BDF(0, 16, 0) INTA PIRQA
116 PCI_BDF(0, 17, 0) INTA PIRQA
117 PCI_BDF(0, 18, 0) INTA PIRQA
118 PCI_BDF(0, 19, 0) INTA PIRQA
119 PCI_BDF(0, 20, 0) INTA PIRQA
120 PCI_BDF(0, 21, 0) INTA PIRQA
121 PCI_BDF(0, 22, 0) INTA PIRQA
122 PCI_BDF(0, 23, 0) INTA PIRQA
123 PCI_BDF(0, 24, 0) INTA PIRQA
124 PCI_BDF(0, 24, 1) INTC PIRQC
125 PCI_BDF(0, 24, 2) INTD PIRQD
126 PCI_BDF(0, 24, 3) INTB PIRQB
127 PCI_BDF(0, 24, 4) INTA PIRQA
128 PCI_BDF(0, 24, 5) INTC PIRQC
129 PCI_BDF(0, 24, 6) INTD PIRQD
130 PCI_BDF(0, 24, 7) INTB PIRQB
131 PCI_BDF(0, 26, 0) INTA PIRQA
132 PCI_BDF(0, 27, 0) INTA PIRQA
133 PCI_BDF(0, 28, 0) INTA PIRQA
134 PCI_BDF(0, 28, 1) INTB PIRQB
135 PCI_BDF(0, 28, 2) INTC PIRQC
136 PCI_BDF(0, 28, 3) INTD PIRQD
137 PCI_BDF(0, 29, 0) INTA PIRQA
138 PCI_BDF(0, 30, 0) INTA PIRQA
139 PCI_BDF(0, 30, 1) INTD PIRQD
140 PCI_BDF(0, 30, 2) INTB PIRQB
141 PCI_BDF(0, 30, 3) INTC PIRQC
142 PCI_BDF(0, 30, 4) INTD PIRQD
143 PCI_BDF(0, 30, 5) INTB PIRQB
144 PCI_BDF(0, 31, 3) INTB PIRQB
145
146 /*
147 * PCIe root ports downstream
148 * interrupts
149 */
150 PCI_BDF(1, 0, 0) INTA PIRQA
151 PCI_BDF(1, 0, 0) INTB PIRQB
152 PCI_BDF(1, 0, 0) INTC PIRQC
153 PCI_BDF(1, 0, 0) INTD PIRQD
154 PCI_BDF(2, 0, 0) INTA PIRQB
155 PCI_BDF(2, 0, 0) INTB PIRQC
156 PCI_BDF(2, 0, 0) INTC PIRQD
157 PCI_BDF(2, 0, 0) INTD PIRQA
158 PCI_BDF(3, 0, 0) INTA PIRQC
159 PCI_BDF(3, 0, 0) INTB PIRQD
160 PCI_BDF(3, 0, 0) INTC PIRQA
161 PCI_BDF(3, 0, 0) INTD PIRQB
162 PCI_BDF(4, 0, 0) INTA PIRQD
163 PCI_BDF(4, 0, 0) INTB PIRQA
164 PCI_BDF(4, 0, 0) INTC PIRQB
165 PCI_BDF(4, 0, 0) INTD PIRQC
166 >;
167 };
168
Bin Meng4f8d4e92016-01-27 00:56:34 -0800169 spi: spi {
Simon Glass32761632016-01-18 20:19:21 -0700170 #address-cells = <1>;
171 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -0800172 compatible = "intel,ich9-spi";
Simon Glass32761632016-01-18 20:19:21 -0700173 spi-flash@0 {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 reg = <0>;
177 compatible = "winbond,w25q64dw",
178 "spi-flash";
179 memory-map = <0xff800000 0x00800000>;
180 rw-mrc-cache {
181 label = "rw-mrc-cache";
182 reg = <0x006e0000 0x00010000>;
183 };
184 };
185 };
Bin Meng6e916cc2016-02-01 01:40:47 -0800186
187 gpioa {
188 compatible = "intel,ich6-gpio";
189 u-boot,dm-pre-reloc;
190 reg = <0 0x20>;
191 bank-name = "A";
Bin Meng59be2c02017-05-07 19:52:29 -0700192 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800193 };
194
195 gpiob {
196 compatible = "intel,ich6-gpio";
197 u-boot,dm-pre-reloc;
198 reg = <0x20 0x20>;
199 bank-name = "B";
Bin Meng59be2c02017-05-07 19:52:29 -0700200 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800201 };
202
203 gpioc {
204 compatible = "intel,ich6-gpio";
205 u-boot,dm-pre-reloc;
206 reg = <0x40 0x20>;
207 bank-name = "C";
Bin Meng59be2c02017-05-07 19:52:29 -0700208 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800209 };
210
211 gpiod {
212 compatible = "intel,ich6-gpio";
213 u-boot,dm-pre-reloc;
214 reg = <0x60 0x20>;
215 bank-name = "D";
Bin Meng59be2c02017-05-07 19:52:29 -0700216 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800217 };
218
219 gpioe {
220 compatible = "intel,ich6-gpio";
221 u-boot,dm-pre-reloc;
222 reg = <0x80 0x20>;
223 bank-name = "E";
Bin Meng59be2c02017-05-07 19:52:29 -0700224 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800225 };
226
227 gpiof {
228 compatible = "intel,ich6-gpio";
229 u-boot,dm-pre-reloc;
230 reg = <0xA0 0x20>;
231 bank-name = "F";
Bin Meng59be2c02017-05-07 19:52:29 -0700232 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800233 };
Bin Meng947391c2015-07-30 03:49:18 -0700234 };
Bin Menge1c49352015-07-30 03:49:17 -0700235 };
236
Andrew Bradford74fdb582015-08-07 08:36:35 -0400237 fsp {
238 compatible = "intel,baytrail-fsp";
Bin Mengfa5905e2017-05-31 01:04:12 -0700239 fsp,mrc-init-tseg-size = <1>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400240 fsp,mrc-init-mmio-size = <0x800>;
241 fsp,mrc-init-spd-addr1 = <0xa0>;
242 fsp,mrc-init-spd-addr2 = <0xa2>;
Bin Meng7bfe2b52016-06-08 05:07:34 -0700243 fsp,emmc-boot-mode = <1>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400244 fsp,enable-sdio;
245 fsp,enable-sdcard;
246 fsp,enable-hsuart1;
247 fsp,enable-spi;
248 fsp,enable-sata;
249 fsp,sata-mode = <1>;
250 fsp,enable-lpe;
251 fsp,lpss-sio-enable-pci-mode;
252 fsp,enable-dma0;
253 fsp,enable-dma1;
254 fsp,enable-i2c0;
255 fsp,enable-i2c1;
256 fsp,enable-i2c2;
257 fsp,enable-i2c3;
258 fsp,enable-i2c4;
259 fsp,enable-i2c5;
260 fsp,enable-i2c6;
261 fsp,enable-pwm0;
262 fsp,enable-pwm1;
263 fsp,igd-dvmt50-pre-alloc = <2>;
264 fsp,aperture-size = <2>;
265 fsp,gtt-size = <2>;
266 fsp,serial-debug-port-address = <0x3f8>;
267 fsp,serial-debug-port-type = <1>;
268 fsp,scc-enable-pci-mode;
269 fsp,os-selection = <4>;
270 fsp,emmc45-ddr50-enabled;
271 fsp,emmc45-retune-timer-value = <8>;
272 fsp,enable-igd;
273 };
274
Bin Menge1c49352015-07-30 03:49:17 -0700275 microcode {
276 update@0 {
277#include "microcode/m0230671117.dtsi"
278 };
Bin Meng35dffd52015-08-15 14:37:50 -0600279 update@1 {
Bin Mengae864552016-05-23 15:25:20 +0800280#include "microcode/m0130673325.dtsi"
Bin Meng35dffd52015-08-15 14:37:50 -0600281 };
282 update@2 {
Bin Mengae864552016-05-23 15:25:20 +0800283#include "microcode/m0130679907.dtsi"
Bin Meng35dffd52015-08-15 14:37:50 -0600284 };
Bin Menge1c49352015-07-30 03:49:17 -0700285 };
286
287};