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git01.mediatek.com / filogic / uboot / fa3d7faf07a9dff2d9073741fff323a2c110696a / . / arch / arm / dts / imx8mq-nitrogen-som.dtsi
blob: 36fc428ebe30008727104a4fe6e840a7098a055e [file] [log] [blame]
Patrick Wildtfa3d7fa2022-01-08 16:04:55 +0100[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2018 Boundary Devices
4 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
5 */
6
7#include "imx8mq.dtsi"
8
9/ {
10 model = "Boundary Devices i.MX8MQ Nitrogen8M";
11 compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
12
13 chosen {
14 stdout-path = &uart1;
15 };
16
17 reg_1p8v: regulator-fixed-1v8 {
18 compatible = "regulator-fixed";
19 regulator-name = "1P8V";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 };
23
24 reg_snvs: regulator-fixed-snvs {
25 compatible = "regulator-fixed";
26 regulator-name = "VDD_SNVS";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 };
30};
31
32&{/opp-table/opp-800000000} {
33 opp-microvolt = <1000000>;
34};
35
36&{/opp-table/opp-1000000000} {
37 opp-microvolt = <1000000>;
38};
39
40&A53_0 {
41 cpu-supply = <&reg_arm_dram>;
42};
43
44&A53_1 {
45 cpu-supply = <&reg_arm_dram>;
46};
47
48&A53_2 {
49 cpu-supply = <&reg_arm_dram>;
50};
51
52&A53_3 {
53 cpu-supply = <&reg_arm_dram>;
54};
55
56&fec1 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_fec1>;
59 phy-mode = "rgmii-id";
60 phy-handle = <&ethphy0>;
61 fsl,magic-packet;
62
63 mdio {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ethphy0: ethernet-phy@4 {
68 compatible = "ethernet-phy-ieee802.3-c22";
69 reg = <4>;
70 interrupt-parent = <&gpio1>;
71 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
72 };
73 };
74};
75
76&i2c1 {
77 clock-frequency = <400000>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_i2c1>;
80 status = "okay";
81
82 i2c-mux@70 {
83 compatible = "nxp,pca9546";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
86 reg = <0x70>;
87 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 i2c1a: i2c@0 {
92 reg = <0>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 reg_arm_dram: regulator@60 {
97 compatible = "fcs,fan53555";
98 reg = <0x60>;
99 regulator-name = "VDD_ARM_DRAM_1V";
100 regulator-min-microvolt = <1000000>;
101 regulator-max-microvolt = <1000000>;
102 regulator-always-on;
103 };
104 };
105
106 i2c1b: i2c@1 {
107 reg = <1>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110
111 reg_dram_1p1v: regulator@60 {
112 compatible = "fcs,fan53555";
113 reg = <0x60>;
114 regulator-name = "NVCC_DRAM_1P1V";
115 regulator-min-microvolt = <1100000>;
116 regulator-max-microvolt = <1100000>;
117 regulator-always-on;
118 };
119 };
120
121 i2c1c: i2c@2 {
122 reg = <2>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 reg_soc_gpu_vpu: regulator@60 {
127 compatible = "fcs,fan53555";
128 reg = <0x60>;
129 regulator-name = "VDD_SOC_GPU_VPU";
130 regulator-min-microvolt = <900000>;
131 regulator-max-microvolt = <900000>;
132 regulator-always-on;
133 };
134 };
135
136 i2c1d: i2c@3 {
137 reg = <3>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
141 };
142};
143
144&pgc_gpu {
145 power-supply = <&reg_soc_gpu_vpu>;
146};
147
148&pgc_vpu {
149 power-supply = <&reg_soc_gpu_vpu>;
150};
151
152&uart1 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uart1>;
155 status = "okay";
156};
157
158&usdhc1 {
159 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
160 assigned-clock-rates = <400000000>;
161 pinctrl-names = "default", "state_100mhz", "state_200mhz";
162 pinctrl-0 = <&pinctrl_usdhc1>;
163 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
164 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
165 vqmmc-supply = <&reg_1p8v>;
166 vmmc-supply = <&reg_snvs>;
167 bus-width = <8>;
168 non-removable;
169 no-mmc-hs400;
170 no-sdio;
171 no-sd;
172 status = "okay";
173};
174
175&wdog1 {
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_wdog>;
178 fsl,ext-reset-output;
179 status = "okay";
180};
181
182&iomuxc {
183 pinctrl_fec1: fec1grp {
184 fsl,pins = <
185 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
186 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
187 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
188 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
189 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
190 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
191 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
192 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
193 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
194 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
195 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
196 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
197 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
198 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
199 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
200 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
201 >;
202 };
203
204 pinctrl_i2c1: i2c1grp {
205 fsl,pins = <
206 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
207 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
208 >;
209 };
210
211 pinctrl_i2c1_pca9546: i2c1-pca9546grp {
212 fsl,pins = <
213 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
214 >;
215 };
216
217 pinctrl_uart1: uart1grp {
218 fsl,pins = <
219 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
220 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
221 >;
222 };
223
224 pinctrl_usdhc1: usdhc1grp {
225 fsl,pins = <
226 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
227 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
228 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
229 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
230 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
231 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
232 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
233 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
234 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
235 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
236 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
237 >;
238 };
239
240 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
241 fsl,pins = <
242 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
243 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
244 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
245 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
246 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
247 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
248 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
249 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
250 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
251 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
252 >;
253 };
254
255 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
256 fsl,pins = <
257 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
258 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
259 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
260 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
261 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
262 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
263 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
264 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
265 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
266 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
267 >;
268 };
269
270 pinctrl_wdog: wdoggrp {
271 fsl,pins = <
272 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
273 >;
274 };
275};