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git01.mediatek.com / filogic / uboot / fa3414d92a3072f2dc4f449c335618b86da74d1e / . / arch / sandbox / dts / test.dts
blob: e2c4971d74025835d6a8217b5916bd7b81752210 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]15 pci0 = &pci;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]16 remoteproc1 = &rproc_1;
17 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]18 rtc0 = &rtc_0;
19 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]20 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]21 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]22 testbus3 = "/some-bus";
23 testfdt0 = "/some-bus/c-test@0";
24 testfdt1 = "/some-bus/c-test@1";
25 testfdt3 = "/b-test";
26 testfdt5 = "/some-bus/c-test@5";
27 testfdt8 = "/a-test";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]28 usb0 = &usb_0;
29 usb1 = &usb_1;
30 usb2 = &usb_2;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]31 };
32
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]33 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]34 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]35 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]36 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]37 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]38 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]39 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
40 <0>, <&gpio_a 12>;
41 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
42 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
43 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]44 };
45
46 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]47 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]48 compatible = "not,compatible";
49 };
50
51 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]52 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]53 };
54
55 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]56 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]57 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]58 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]59 ping-add = <3>;
60 };
61
62 some-bus {
63 #address-cells = <1>;
64 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]65 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]66 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]67 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]68 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]69 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]70 compatible = "denx,u-boot-fdt-test";
71 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]72 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]73 ping-add = <5>;
74 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]75 c-test@0 {
76 compatible = "denx,u-boot-fdt-test";
77 reg = <0>;
78 ping-expect = <6>;
79 ping-add = <6>;
80 };
81 c-test@1 {
82 compatible = "denx,u-boot-fdt-test";
83 reg = <1>;
84 ping-expect = <7>;
85 ping-add = <7>;
86 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 };
88
89 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]90 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]91 ping-expect = <6>;
92 ping-add = <6>;
93 compatible = "google,another-fdt-test";
94 };
95
96 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]97 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]98 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]99 ping-add = <6>;
100 compatible = "google,another-fdt-test";
101 };
102
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]103 f-test {
104 compatible = "denx,u-boot-fdt-test";
105 };
106
107 g-test {
108 compatible = "denx,u-boot-fdt-test";
109 };
110
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]111 clk@0 {
112 compatible = "sandbox,clk";
113 };
114
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]115 eth@10002000 {
116 compatible = "sandbox,eth";
117 reg = <0x10002000 0x1000>;
118 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
119 };
120
121 eth_5: eth@10003000 {
122 compatible = "sandbox,eth";
123 reg = <0x10003000 0x1000>;
124 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
125 };
126
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]127 eth_3: sbe5 {
128 compatible = "sandbox,eth";
129 reg = <0x10005000 0x1000>;
130 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>;
131 };
132
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]133 eth@10004000 {
134 compatible = "sandbox,eth";
135 reg = <0x10004000 0x1000>;
136 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
137 };
138
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]139 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]140 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]141 gpio-controller;
142 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]143 gpio-bank-name = "a";
144 num-gpios = <20>;
145 };
146
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]147 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]148 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]149 gpio-controller;
150 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]151 gpio-bank-name = "b";
152 num-gpios = <10>;
153 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]154
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]155 i2c@0 {
156 #address-cells = <1>;
157 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]158 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]159 compatible = "sandbox,i2c";
160 clock-frequency = <100000>;
161 eeprom@2c {
162 reg = <0x2c>;
163 compatible = "i2c-eeprom";
164 emul {
165 compatible = "sandbox,i2c-eeprom";
166 sandbox,filename = "i2c.bin";
167 sandbox,size = <256>;
168 };
169 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]170
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]171 rtc_0: rtc@43 {
172 reg = <0x43>;
173 compatible = "sandbox-rtc";
174 emul {
175 compatible = "sandbox,i2c-rtc";
176 };
177 };
178
179 rtc_1: rtc@61 {
180 reg = <0x61>;
181 compatible = "sandbox-rtc";
182 emul {
183 compatible = "sandbox,i2c-rtc";
184 };
185 };
186
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]187 sandbox_pmic: sandbox_pmic {
188 reg = <0x40>;
189 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]190 };
191
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]192 adc@0 {
193 compatible = "sandbox,adc";
194 vdd-supply = <&buck2>;
195 vss-microvolts = <0>;
196 };
197
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]198 leds {
199 compatible = "gpio-leds";
200
201 iracibble {
202 gpios = <&gpio_a 1 0>;
203 label = "sandbox:red";
204 };
205
206 martinet {
207 gpios = <&gpio_a 2 0>;
208 label = "sandbox:green";
209 };
210 };
211
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]212 mmc {
213 compatible = "sandbox,mmc";
214 };
215
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]216 pci: pci-controller {
217 compatible = "sandbox,pci";
218 device_type = "pci";
219 #address-cells = <3>;
220 #size-cells = <2>;
221 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
222 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
223 pci@1f,0 {
224 compatible = "pci-generic";
225 reg = <0xf800 0 0 0 0>;
226 emul@1f,0 {
227 compatible = "sandbox,swap-case";
228 };
229 };
230 };
231
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]232 ram {
233 compatible = "sandbox,ram";
234 };
235
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]236 reset@0 {
237 compatible = "sandbox,warm-reset";
238 };
239
240 reset@1 {
241 compatible = "sandbox,reset";
242 };
243
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]244 rproc_1: rproc@1 {
245 compatible = "sandbox,test-processor";
246 remoteproc-name = "remoteproc-test-dev1";
247 };
248
249 rproc_2: rproc@2 {
250 compatible = "sandbox,test-processor";
251 internal-memory-mapped;
252 remoteproc-name = "remoteproc-test-dev2";
253 };
254
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]255 spi@0 {
256 #address-cells = <1>;
257 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]258 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]259 compatible = "sandbox,spi";
260 cs-gpios = <0>, <&gpio_a 0>;
261 spi.bin@0 {
262 reg = <0>;
263 compatible = "spansion,m25p16", "spi-flash";
264 spi-max-frequency = <40000000>;
265 sandbox,filename = "spi.bin";
266 };
267 };
268
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]269 syscon@0 {
270 compatible = "sandbox,syscon0";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]271 reg = <0x10 4>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]272 };
273
274 syscon@1 {
275 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]276 reg = <0x20 5
277 0x28 6
278 0x30 7
279 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]280 };
281
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]282 uart0: serial {
283 compatible = "sandbox,serial";
284 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]285 };
286
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]287 usb_0: usb@0 {
288 compatible = "sandbox,usb";
289 status = "disabled";
290 hub {
291 compatible = "sandbox,usb-hub";
292 #address-cells = <1>;
293 #size-cells = <0>;
294 flash-stick {
295 reg = <0>;
296 compatible = "sandbox,usb-flash";
297 };
298 };
299 };
300
301 usb_1: usb@1 {
302 compatible = "sandbox,usb";
303 hub {
304 compatible = "usb-hub";
305 usb,device-class = <9>;
306 hub-emul {
307 compatible = "sandbox,usb-hub";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 flash-stick {
311 reg = <0>;
312 compatible = "sandbox,usb-flash";
313 sandbox,filepath = "testflash.bin";
314 };
315
316 };
317 };
318 };
319
320 usb_2: usb@2 {
321 compatible = "sandbox,usb";
322 status = "disabled";
323 };
324
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]325};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]326
327#include "sandbox_pmic.dtsi"