blob: 034a349236e828cc8937b4962926929568ce7386 [file] [log] [blame]
Peng Fanc47e09d2019-12-30 17:46:21 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06007#include <env.h>
Peng Fanc47e09d2019-12-30 17:46:21 +08008#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080010#include <asm/mach-imx/iomux-v3.h>
11#include <asm-generic/gpio.h>
12#include <asm/arch/imx8mp_pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/mach-imx/gpio.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
19#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
20
21static iomux_v3_cfg_t const uart_pads[] = {
22 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
23 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
24};
25
26static iomux_v3_cfg_t const wdog_pads[] = {
27 MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
28};
29
30int board_early_init_f(void)
31{
32 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
33
34 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
35
36 set_wdog_reset(wdog);
37
38 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
39
40 return 0;
41}
42
Peng Fanc47e09d2019-12-30 17:46:21 +080043int board_init(void)
44{
45 return 0;
46}
47
48int board_late_init(void)
49{
50#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
51 env_set("board_name", "EVK");
52 env_set("board_rev", "iMX8MP");
53#endif
54
55 return 0;
56}