blob: 722dff1f64c50f6ed4b46fac24d8b221a8e86525 [file] [log] [blame]
Mark Kettenis58d51272021-10-23 16:58:03 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <efi_loader.h>
Mark Kettenis74ec0482022-03-21 22:41:18 +01009#include <lmb.h>
Mark Kettenis58d51272021-10-23 16:58:03 +020010
11#include <asm/armv8/mmu.h>
12#include <asm/global_data.h>
13#include <asm/io.h>
14#include <asm/system.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
Mark Kettenis73c82c82022-02-08 22:00:09 +010018/* Apple M1 */
19
20static struct mm_region t8103_mem_map[] = {
Mark Kettenis58d51272021-10-23 16:58:03 +020021 {
22 /* I/O */
23 .virt = 0x200000000,
24 .phys = 0x200000000,
Mark Kettenis73c82c82022-02-08 22:00:09 +010025 .size = 2UL * SZ_1G,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 PTE_BLOCK_NON_SHARE |
28 PTE_BLOCK_PXN | PTE_BLOCK_UXN
29 }, {
30 /* I/O */
31 .virt = 0x380000000,
32 .phys = 0x380000000,
33 .size = SZ_1G,
Mark Kettenis58d51272021-10-23 16:58:03 +020034 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 PTE_BLOCK_NON_SHARE |
36 PTE_BLOCK_PXN | PTE_BLOCK_UXN
37 }, {
38 /* I/O */
39 .virt = 0x500000000,
40 .phys = 0x500000000,
Mark Kettenis73c82c82022-02-08 22:00:09 +010041 .size = SZ_1G,
Mark Kettenis58d51272021-10-23 16:58:03 +020042 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43 PTE_BLOCK_NON_SHARE |
44 PTE_BLOCK_PXN | PTE_BLOCK_UXN
45 }, {
46 /* I/O */
47 .virt = 0x680000000,
48 .phys = 0x680000000,
49 .size = SZ_512M,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_NON_SHARE |
52 PTE_BLOCK_PXN | PTE_BLOCK_UXN
53 }, {
54 /* PCIE */
55 .virt = 0x6a0000000,
56 .phys = 0x6a0000000,
57 .size = SZ_512M,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
59 PTE_BLOCK_INNER_SHARE |
60 PTE_BLOCK_PXN | PTE_BLOCK_UXN
61 }, {
62 /* PCIE */
63 .virt = 0x6c0000000,
64 .phys = 0x6c0000000,
65 .size = SZ_1G,
66 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
67 PTE_BLOCK_INNER_SHARE |
68 PTE_BLOCK_PXN | PTE_BLOCK_UXN
69 }, {
70 /* RAM */
71 .virt = 0x800000000,
72 .phys = 0x800000000,
73 .size = 8UL * SZ_1G,
74 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
75 PTE_BLOCK_INNER_SHARE
76 }, {
Mark Kettenis73c82c82022-02-08 22:00:09 +010077 /* Framebuffer */
78 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
79 PTE_BLOCK_INNER_SHARE |
80 PTE_BLOCK_PXN | PTE_BLOCK_UXN
81 }, {
82 /* List terminator */
Mark Kettenis58d51272021-10-23 16:58:03 +020083 0,
Mark Kettenis73c82c82022-02-08 22:00:09 +010084 }
85};
86
87/* Apple M1 Pro/Max */
88
89static struct mm_region t6000_mem_map[] = {
90 {
91 /* I/O */
92 .virt = 0x280000000,
93 .phys = 0x280000000,
94 .size = SZ_1G,
95 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
96 PTE_BLOCK_NON_SHARE |
97 PTE_BLOCK_PXN | PTE_BLOCK_UXN
98 }, {
99 /* I/O */
100 .virt = 0x380000000,
101 .phys = 0x380000000,
102 .size = SZ_1G,
103 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
104 PTE_BLOCK_NON_SHARE |
105 PTE_BLOCK_PXN | PTE_BLOCK_UXN
106 }, {
107 /* I/O */
108 .virt = 0x580000000,
109 .phys = 0x580000000,
110 .size = SZ_512M,
111 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
112 PTE_BLOCK_NON_SHARE |
113 PTE_BLOCK_PXN | PTE_BLOCK_UXN
114 }, {
115 /* PCIE */
116 .virt = 0x5a0000000,
117 .phys = 0x5a0000000,
118 .size = SZ_512M,
119 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
120 PTE_BLOCK_INNER_SHARE |
121 PTE_BLOCK_PXN | PTE_BLOCK_UXN
122 }, {
123 /* PCIE */
124 .virt = 0x5c0000000,
125 .phys = 0x5c0000000,
126 .size = SZ_1G,
127 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
128 PTE_BLOCK_INNER_SHARE |
129 PTE_BLOCK_PXN | PTE_BLOCK_UXN
130 }, {
131 /* I/O */
132 .virt = 0x700000000,
133 .phys = 0x700000000,
134 .size = SZ_1G,
135 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
136 PTE_BLOCK_NON_SHARE |
137 PTE_BLOCK_PXN | PTE_BLOCK_UXN
138 }, {
139 /* I/O */
140 .virt = 0xb00000000,
141 .phys = 0xb00000000,
142 .size = SZ_1G,
143 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
144 PTE_BLOCK_NON_SHARE |
145 PTE_BLOCK_PXN | PTE_BLOCK_UXN
146 }, {
147 /* I/O */
148 .virt = 0xf00000000,
149 .phys = 0xf00000000,
150 .size = SZ_1G,
151 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
152 PTE_BLOCK_NON_SHARE |
153 PTE_BLOCK_PXN | PTE_BLOCK_UXN
154 }, {
155 /* I/O */
156 .virt = 0x1300000000,
157 .phys = 0x1300000000,
158 .size = SZ_1G,
159 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
160 PTE_BLOCK_NON_SHARE |
161 PTE_BLOCK_PXN | PTE_BLOCK_UXN
162 }, {
163 /* RAM */
164 .virt = 0x10000000000,
165 .phys = 0x10000000000,
166 .size = 16UL * SZ_1G,
167 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
168 PTE_BLOCK_INNER_SHARE
169 }, {
170 /* Framebuffer */
171 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
172 PTE_BLOCK_INNER_SHARE |
173 PTE_BLOCK_PXN | PTE_BLOCK_UXN
Mark Kettenis58d51272021-10-23 16:58:03 +0200174 }, {
175 /* List terminator */
176 0,
177 }
178};
179
Mark Kettenis73c82c82022-02-08 22:00:09 +0100180struct mm_region *mem_map;
Mark Kettenis58d51272021-10-23 16:58:03 +0200181
182int board_init(void)
183{
184 return 0;
185}
186
187int dram_init(void)
188{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100189 return fdtdec_setup_mem_size_base();
190}
191
192int dram_init_banksize(void)
193{
194 return fdtdec_setup_memory_banksize();
195}
196
197extern long fw_dtb_pointer;
198
199void *board_fdt_blob_setup(int *err)
200{
201 /* Return DTB pointer passed by m1n1 */
202 *err = 0;
203 return (void *)fw_dtb_pointer;
204}
205
206void build_mem_map(void)
207{
Mark Kettenis58d51272021-10-23 16:58:03 +0200208 ofnode node;
Mark Kettenis58d51272021-10-23 16:58:03 +0200209 fdt_addr_t base;
210 fdt_size_t size;
Mark Kettenis73c82c82022-02-08 22:00:09 +0100211 int i;
212
213 if (of_machine_is_compatible("apple,t8103"))
214 mem_map = t8103_mem_map;
215 else if (of_machine_is_compatible("apple,t6000"))
216 mem_map = t6000_mem_map;
217 else if (of_machine_is_compatible("apple,t6001"))
218 mem_map = t6000_mem_map;
219 else
220 panic("Unsupported SoC\n");
Mark Kettenis58d51272021-10-23 16:58:03 +0200221
Mark Kettenis73c82c82022-02-08 22:00:09 +0100222 /* Find list terminator. */
223 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
224 ;
225
226 /* Align RAM mapping to page boundaries */
227 base = gd->bd->bi_dram[0].start;
228 size = gd->bd->bi_dram[0].size;
229 size += (base - ALIGN_DOWN(base, SZ_4K));
230 base = ALIGN_DOWN(base, SZ_4K);
231 size = ALIGN(size, SZ_4K);
Mark Kettenis58d51272021-10-23 16:58:03 +0200232
233 /* Update RAM mapping */
Mark Kettenis73c82c82022-02-08 22:00:09 +0100234 mem_map[i - 2].virt = base;
235 mem_map[i - 2].phys = base;
236 mem_map[i - 2].size = size;
Mark Kettenis58d51272021-10-23 16:58:03 +0200237
238 node = ofnode_path("/chosen/framebuffer");
239 if (!ofnode_valid(node))
Mark Kettenis73c82c82022-02-08 22:00:09 +0100240 return;
Mark Kettenis58d51272021-10-23 16:58:03 +0200241
242 base = ofnode_get_addr_size(node, "reg", &size);
243 if (base == FDT_ADDR_T_NONE)
Mark Kettenis73c82c82022-02-08 22:00:09 +0100244 return;
Mark Kettenis58d51272021-10-23 16:58:03 +0200245
Mark Kettenis73c82c82022-02-08 22:00:09 +0100246 /* Align framebuffer mapping to page boundaries */
247 size += (base - ALIGN_DOWN(base, SZ_4K));
248 base = ALIGN_DOWN(base, SZ_4K);
249 size = ALIGN(size, SZ_4K);
Mark Kettenis58d51272021-10-23 16:58:03 +0200250
Mark Kettenis73c82c82022-02-08 22:00:09 +0100251 /* Add framebuffer mapping */
252 mem_map[i - 1].virt = base;
253 mem_map[i - 1].phys = base;
254 mem_map[i - 1].size = size;
Mark Kettenis58d51272021-10-23 16:58:03 +0200255}
256
Mark Kettenis73c82c82022-02-08 22:00:09 +0100257void enable_caches(void)
Mark Kettenis58d51272021-10-23 16:58:03 +0200258{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100259 build_mem_map();
Mark Kettenis58d51272021-10-23 16:58:03 +0200260
Mark Kettenis73c82c82022-02-08 22:00:09 +0100261 icache_enable();
262 dcache_enable();
Mark Kettenis58d51272021-10-23 16:58:03 +0200263}
264
Mark Kettenis73c82c82022-02-08 22:00:09 +0100265u64 get_page_table_size(void)
Mark Kettenis58d51272021-10-23 16:58:03 +0200266{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100267 return SZ_256K;
Mark Kettenis58d51272021-10-23 16:58:03 +0200268}
Janne Grunau3a216712022-02-19 14:05:19 +0100269
Mark Kettenis74ec0482022-03-21 22:41:18 +0100270#define KERNEL_COMP_SIZE SZ_128M
271
Janne Grunau3a216712022-02-19 14:05:19 +0100272int board_late_init(void)
273{
Mark Kettenis74ec0482022-03-21 22:41:18 +0100274 struct lmb lmb;
Janne Grunau3a216712022-02-19 14:05:19 +0100275 u32 status = 0;
276
Mark Kettenis74ec0482022-03-21 22:41:18 +0100277 lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
Janne Grunau3a216712022-02-19 14:05:19 +0100278
279 /* somewhat based on the Linux Kernel boot requirements:
280 * align by 2M and maximal FDT size 2M
281 */
Mark Kettenis74ec0482022-03-21 22:41:18 +0100282 status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M));
283 status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M));
284 status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M));
285 status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M));
286 status |= env_set_hex("kernel_comp_addr_r",
287 lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M));
288 status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
289 status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M));
290 status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M));
Janne Grunau3a216712022-02-19 14:05:19 +0100291
292 if (status)
293 log_warning("late_init: Failed to set run time variables\n");
294
295 return 0;
296}