blob: 6091f8cef194a1b06fc7c248ccbf6fc995efac2f [file] [log] [blame]
Mike Frysinger94bae5c2008-03-30 15:46:13 -04001/*
2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
6 *
7 * Copyright (c) 2004-2008 Analog Devices Inc.
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12#include <config.h>
13#include <asm/blackfin.h>
14#include <asm/mach-common/bits/bootrom.h>
15#include <asm/mach-common/bits/ebiu.h>
16#include <asm/mach-common/bits/pll.h>
17#include <asm/mach-common/bits/uart.h>
18
19#define BFIN_IN_INITCODE
20#include "serial.h"
21
22__attribute__((always_inline))
23static inline uint32_t serial_init(void)
24{
25#ifdef __ADSPBF54x__
26# ifdef BFIN_BOOT_UART_USE_RTS
27# define BFIN_UART_USE_RTS 1
28# else
29# define BFIN_UART_USE_RTS 0
30# endif
31 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
32 size_t i;
33
34 /* force RTS rather than relying on auto RTS */
35 bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
36
37 /* Wait for the line to clear up. We cannot rely on UART
38 * registers as none of them reflect the status of the RSR.
39 * Instead, we'll sleep for ~10 bit times at 9600 baud.
40 * We can precalc things here by assuming boot values for
41 * PLL rather than loading registers and calculating.
42 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
43 * EDB0 = 0
44 * Divisor = (SCLK / baud) / 16
45 * SCLK = baud * 16 * Divisor
46 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
47 * CCLK = (16 * Divisor * 5) * (9600 / 10)
48 * In reality, this will probably be just about 1 second delay,
49 * so assuming 9600 baud is OK (both as a very low and too high
50 * speed as this will buffer things enough).
51 */
52#define _NUMBITS (10) /* how many bits to delay */
53#define _LOWBAUD (9600) /* low baud rate */
54#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
55#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
56#define _NUMINS (3) /* how many instructions in loop */
57#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
58 i = _CCLK;
59 while (i--)
60 asm volatile("" : : : "memory");
61 }
62#endif
63
Mike Frysinger83c31fc2008-10-20 21:08:54 -040064 uint32_t old_baud;
65 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
66 old_baud = serial_early_get_baud();
67 else
68 old_baud = CONFIG_BAUDRATE;
Mike Frysinger94bae5c2008-03-30 15:46:13 -040069
70 if (BFIN_DEBUG_EARLY_SERIAL) {
71 serial_early_init();
72
73 /* If the UART is off, that means we need to program
74 * the baud rate ourselves initially.
75 */
76 if (!old_baud) {
77 old_baud = CONFIG_BAUDRATE;
78 serial_early_set_baud(CONFIG_BAUDRATE);
79 }
80 }
81
82 return old_baud;
83}
84
85__attribute__((always_inline))
86static inline void serial_deinit(void)
87{
88#ifdef __ADSPBF54x__
89 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
90 /* clear forced RTS rather than relying on auto RTS */
91 bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
92 }
93#endif
94}
95
96/* We need to reset the baud rate when we have early debug turned on
97 * or when we are booting over the UART.
98 * XXX: we should fix this to calc the old baud and restore it rather
99 * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
100 * to figure out how to avoid the division in the baud calc ...
101 */
102__attribute__((always_inline))
103static inline void serial_reset_baud(uint32_t baud)
104{
105 if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
106 return;
107
108#ifndef CONFIG_LDR_LOAD_BAUD
109# define CONFIG_LDR_LOAD_BAUD 115200
110#endif
111
112 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
113 serial_early_set_baud(baud);
114 else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
115 serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
116 else
117 serial_early_set_baud(CONFIG_BAUDRATE);
118}
119
120__attribute__((always_inline))
121static inline void serial_putc(char c)
122{
123 if (!BFIN_DEBUG_EARLY_SERIAL)
124 return;
125
126 if (c == '\n')
127 *pUART_THR = '\r';
128
129 *pUART_THR = c;
130
131 while (!(*pUART_LSR & TEMT))
132 continue;
133}
134
135
136/* Max SCLK can be 133MHz ... dividing that by 4 gives
137 * us a freq of 33MHz for SPI which should generally be
138 * slow enough for the slow reads the bootrom uses.
139 */
140#ifndef CONFIG_SPI_BAUD_INITBLOCK
141# define CONFIG_SPI_BAUD_INITBLOCK 4
142#endif
143
144/* PLL_DIV defines */
145#ifndef CONFIG_PLL_DIV_VAL
146# if (CONFIG_CCLK_DIV == 1)
147# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
148# elif (CONFIG_CCLK_DIV == 2)
149# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
150# elif (CONFIG_CCLK_DIV == 4)
151# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
152# elif (CONFIG_CCLK_DIV == 8)
153# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
154# else
155# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
156# endif
157# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
158#endif
159
160#ifndef CONFIG_PLL_LOCKCNT_VAL
161# define CONFIG_PLL_LOCKCNT_VAL 0x0300
162#endif
163
164#ifndef CONFIG_PLL_CTL_VAL
Mike Frysingerc13fc442008-06-01 01:26:29 -0400165# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400166#endif
167
168#ifndef CONFIG_EBIU_RSTCTL_VAL
169# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
170#endif
171
172#ifndef CONFIG_EBIU_MBSCTL_VAL
173# define CONFIG_EBIU_MBSCTL_VAL 0
174#endif
175
176/* Make sure our voltage value is sane so we don't blow up! */
177#ifndef CONFIG_VR_CTL_VAL
178# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
179# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
180# define CCLK_VLEV_120 400000000
181# define CCLK_VLEV_125 533000000
182# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
183# define CCLK_VLEV_120 401000000
184# define CCLK_VLEV_125 401000000
185# elif defined(__ADSPBF561__)
186# define CCLK_VLEV_120 300000000
187# define CCLK_VLEV_125 501000000
188# endif
189# if BFIN_CCLK < CCLK_VLEV_120
190# define CONFIG_VR_CTL_VLEV VLEV_120
191# elif BFIN_CCLK < CCLK_VLEV_125
192# define CONFIG_VR_CTL_VLEV VLEV_125
193# else
194# define CONFIG_VR_CTL_VLEV VLEV_130
195# endif
196# if defined(__ADSPBF52x__) /* TBD; use default */
197# undef CONFIG_VR_CTL_VLEV
198# define CONFIG_VR_CTL_VLEV VLEV_110
199# elif defined(__ADSPBF54x__) /* TBD; use default */
200# undef CONFIG_VR_CTL_VLEV
201# define CONFIG_VR_CTL_VLEV VLEV_120
202# endif
203
204# ifdef CONFIG_BFIN_MAC
205# define CONFIG_VR_CTL_CLKBUF CLKBUFOE
206# else
207# define CONFIG_VR_CTL_CLKBUF 0
208# endif
209
210# if defined(__ADSPBF52x__)
211# define CONFIG_VR_CTL_FREQ FREQ_1000
212# else
213# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
214# endif
215
216# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
217#endif
218
219__attribute__((saveall))
220void initcode(ADI_BOOT_DATA *bootstruct)
221{
222 uint32_t old_baud = serial_init();
223
224#ifdef CONFIG_HW_WATCHDOG
225# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
226# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
227# endif
228 /* Program the watchdog with an initial timeout of ~20 seconds.
229 * Hopefully that should be long enough to load the u-boot LDR
230 * (from wherever) and then the common u-boot code can take over.
231 * In bypass mode, the start.S would have already set a much lower
232 * timeout, so don't clobber that.
233 */
234 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
235 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
236 bfin_write_WDOG_CTL(0);
237 }
238#endif
239
240 serial_putc('S');
241
242 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
243 * fast read, so we need to slow down the SPI clock a lot more during
244 * boot. Once we switch over to u-boot's SPI flash driver, we'll
245 * increase the speed appropriately.
246 */
247 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
248#ifdef SPI0_BAUD
249 bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
250#else
251 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
252#endif
253
254 serial_putc('B');
255
256 /* Disable all peripheral wakeups except for the PLL event. */
257#ifdef SIC_IWR0
258 bfin_write_SIC_IWR0(1);
259 bfin_write_SIC_IWR1(0);
260# ifdef SIC_IWR2
261 bfin_write_SIC_IWR2(0);
262# endif
263#elif defined(SICA_IWR0)
264 bfin_write_SICA_IWR0(1);
265 bfin_write_SICA_IWR1(0);
266#else
267 bfin_write_SIC_IWR(1);
268#endif
269
270 serial_putc('L');
271
272 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
273
274 serial_putc('A');
275
276 /* Only reprogram when needed to avoid triggering unnecessary
277 * PLL relock sequences.
278 */
279 if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
280 serial_putc('!');
281 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
282 asm("idle;");
283 }
284
285 serial_putc('C');
286
287 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
288
289 serial_putc('K');
290
291 /* Only reprogram when needed to avoid triggering unnecessary
292 * PLL relock sequences.
293 */
294 if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
295 serial_putc('!');
296 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
297 asm("idle;");
298 }
299
300 /* Since we've changed the SCLK above, we may need to update
301 * the UART divisors (UART baud rates are based on SCLK).
302 */
303 serial_reset_baud(old_baud);
304
305 serial_putc('F');
306
307 /* Program the async banks controller. */
308 bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
309 bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
310 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
311
312#ifdef EBIU_MODE
313 /* Not all parts have these additional MMRs. */
314 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
315 bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
316 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
317#endif
318
319 serial_putc('I');
320
321 /* Program the external memory controller. */
322#ifdef EBIU_RSTCTL
323 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
324 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
325 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
326 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
327# ifdef CONFIG_EBIU_DDRCTL3_VAL
328 /* default is disable, so don't need to force this */
329 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
330# endif
331#else
332 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
333 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
334 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
335#endif
336
337 serial_putc('N');
338
339 /* Restore all peripheral wakeups. */
340#ifdef SIC_IWR0
341 bfin_write_SIC_IWR0(-1);
342 bfin_write_SIC_IWR1(-1);
343# ifdef SIC_IWR2
344 bfin_write_SIC_IWR2(-1);
345# endif
346#elif defined(SICA_IWR0)
347 bfin_write_SICA_IWR0(-1);
348 bfin_write_SICA_IWR1(-1);
349#else
350 bfin_write_SIC_IWR(-1);
351#endif
352
353 serial_putc('>');
354 serial_putc('\n');
355
356 serial_deinit();
357}