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Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +09001/*
2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +09007 */
8
9#ifndef __SH7785LCR_H
10#define __SH7785LCR_H
11
12#undef DEBUG
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090013#define CONFIG_CPU_SH7785 1
14#define CONFIG_SH7785LCR 1
15
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090016#define CONFIG_CMD_PCI
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090017#define CONFIG_CMD_SDRAM
Nobuhiro Iwamatsu30439052010-12-08 14:00:24 +090018#define CONFIG_CMD_SH_ZIMAGEBOOT
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090019
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090020#define CONFIG_DOS_PARTITION
21#define CONFIG_MAC_PARTITION
22
23#define CONFIG_BAUDRATE 115200
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090024#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
25
26#define CONFIG_EXTRA_ENV_SETTINGS \
27 "bootdevice=0:1\0" \
28 "usbload=usb reset;usbboot;usb stop;bootm\0"
29
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090030#undef CONFIG_SHOW_BOOT_PROGRESS
31
32/* MEMORY */
Yoshihiro Shimoda22dc9ec2009-03-03 15:11:17 +090033#if defined(CONFIG_SH_32BIT)
Nobuhiro Iwamatsu2efe42b2011-01-17 21:02:16 +090034#define CONFIG_SYS_TEXT_BASE 0x8FF80000
Nobuhiro Iwamatsuf0eb8152010-10-05 16:58:05 +090035/* 0x40000000 - 0x47FFFFFF does not use */
36#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
37#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
38#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
Yoshihiro Shimoda22dc9ec2009-03-03 15:11:17 +090039#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
40#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
41#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
42#define SH7785LCR_USB_BASE (0xa6000000)
43#else
Nobuhiro Iwamatsu2efe42b2011-01-17 21:02:16 +090044#define CONFIG_SYS_TEXT_BASE 0x0FF80000
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090045#define SH7785LCR_SDRAM_BASE (0x08000000)
46#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
47#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
48#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
49#define SH7785LCR_USB_BASE (0xb4000000)
Yoshihiro Shimoda22dc9ec2009-03-03 15:11:17 +090050#endif
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090051
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_CBSIZE 256
54#define CONFIG_SYS_PBSIZE 256
55#define CONFIG_SYS_MAXARGS 16
56#define CONFIG_SYS_BARGSIZE 512
57#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090058
59/* SCIF */
Nobuhiro Iwamatsu85603f42008-08-28 14:53:31 +090060#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090061#define CONFIG_CONS_SCIF1 1
62#define CONFIG_SCIF_EXT_CLOCK 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#undef CONFIG_SYS_CONSOLE_INFO_QUIET
64#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
65#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090066
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
68#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090069 (SH7785LCR_SDRAM_SIZE) - \
70 4 * 1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#undef CONFIG_SYS_ALT_MEMTEST
72#undef CONFIG_SYS_MEMTEST_SCRATCH
73#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
76#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
77#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090078
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
80#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
81#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090083
84/* FLASH */
Nobuhiro Iwamatsu85603f42008-08-28 14:53:31 +090085#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_FLASH_CFI
87#undef CONFIG_SYS_FLASH_QUIET_TEST
88#define CONFIG_SYS_FLASH_EMPTY_INFO
89#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
90#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090091
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_MAX_FLASH_BANKS 1
93#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +090094 (0 * SH7785LCR_FLASH_BANK_SIZE) }
95
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
97#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
98#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
99#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#undef CONFIG_SYS_FLASH_PROTECTION
102#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900103
104/* R8A66597 */
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900105#define CONFIG_USB_R8A66597_HCD
106#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
107#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
108#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
109#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
110
111/* PCI Controller */
112#define CONFIG_PCI
113#define CONFIG_SH4_PCI
114#define CONFIG_SH7780_PCI
Yoshihiro Shimoda22dc9ec2009-03-03 15:11:17 +0900115#if defined(CONFIG_SH_32BIT)
116#define CONFIG_SH7780_PCI_LSR 0x1ff00001
117#define CONFIG_SH7780_PCI_LAR 0x5f000000
118#define CONFIG_SH7780_PCI_BAR 0x5f000000
119#else
Yoshihiro Shimoda30e055b2009-02-25 14:26:42 +0900120#define CONFIG_SH7780_PCI_LSR 0x07f00001
121#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
122#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yoshihiro Shimoda22dc9ec2009-03-03 15:11:17 +0900123#endif
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900124#define CONFIG_PCI_PNP
125#define CONFIG_PCI_SCAN_SHOW 1
126
127#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
128#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
129#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
130
131#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
132#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
133#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
134
Yoshihiro Shimoda22dc9ec2009-03-03 15:11:17 +0900135#if defined(CONFIG_SH_32BIT)
136#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
137#else
Yoshihiro Shimodaf9fc4402009-02-25 14:26:55 +0900138#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimoda22dc9ec2009-03-03 15:11:17 +0900139#endif
140#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimodaf9fc4402009-02-25 14:26:55 +0900141#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
142
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900143/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200144#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900145#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200146#define CONFIG_ENV_SECT_SIZE (256 * 1024)
147#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
149#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200150#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900151
152/* Board Clock */
153/* The SCIF used external clock. system clock only used timer. */
154#define CONFIG_SYS_CLK_FREQ 50000000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +0900155#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
156#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200157#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu52f73c02008-08-31 22:45:08 +0900158
159#endif /* __SH7785LCR_H */