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Stefan Roese9b1e2312014-10-22 12:13:19 +02001/*
2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CONFIG_DB_MV7846MP_GP_H
8#define _CONFIG_DB_MV7846MP_GP_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
Stefan Roese9b1e2312014-10-22 12:13:19 +020013#define CONFIG_DISPLAY_BOARDINFO_LATE
14
Stefan Roese3dbf35c2015-08-06 14:27:36 +020015/*
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
18 * U-Boot into it.
19 */
20#define CONFIG_SYS_TEXT_BASE 0x00800000
Stefan Roese9b1e2312014-10-22 12:13:19 +020021#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
22
23/*
24 * Commands configuration
25 */
26#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
Stefan Roese9b1e2312014-10-22 12:13:19 +020027#define CONFIG_CMD_ENV
Stefan Roese9b1e2312014-10-22 12:13:19 +020028
29/* I2C */
30#define CONFIG_SYS_I2C
31#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +020032#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese9b1e2312014-10-22 12:13:19 +020033#define CONFIG_SYS_I2C_SLAVE 0x0
34#define CONFIG_SYS_I2C_SPEED 100000
35
36/* SPI NOR flash default params, used by sf commands */
37#define CONFIG_SF_DEFAULT_SPEED 1000000
38#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roese9b1e2312014-10-22 12:13:19 +020039
40/* Environment in SPI NOR flash */
41#define CONFIG_ENV_IS_IN_SPI_FLASH
42#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
43#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
44#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
45
46#define CONFIG_PHY_MARVELL /* there is a marvell phy */
Stefan Roese9b1e2312014-10-22 12:13:19 +020047#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roese9b1e2312014-10-22 12:13:19 +020048
49#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
50#define CONFIG_SYS_ALT_MEMTEST
51
52/*
53 * mv-common.h should be defined after CMD configs since it used them
54 * to enable certain macros
55 */
56#include "mv-common.h"
57
Stefan Roese1a16a0c2015-01-19 11:33:47 +010058/*
59 * Memory layout while starting into the bin_hdr via the
60 * BootROM:
61 *
62 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
63 * 0x4000.4030 bin_hdr start address
64 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
65 * 0x4007.fffc BootROM stack top
66 *
67 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
68 * L2 cache thus cannot be used.
69 */
70
71/* SPL */
72/* Defines for SPL */
73#define CONFIG_SPL_FRAMEWORK
74#define CONFIG_SPL_TEXT_BASE 0x40004030
75#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
76
77#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
78#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
79
Stefan Roese83097cf2015-11-25 07:37:00 +010080#ifdef CONFIG_SPL_BUILD
81#define CONFIG_SYS_MALLOC_SIMPLE
82#endif
Stefan Roese1a16a0c2015-01-19 11:33:47 +010083
84#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
85#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
86
Stefan Roese1a16a0c2015-01-19 11:33:47 +010087/* SPL related SPI defines */
Stefan Roese1a16a0c2015-01-19 11:33:47 +010088#define CONFIG_SPL_SPI_LOAD
Stefan Roese1a16a0c2015-01-19 11:33:47 +010089#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
90
91/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roese1a16a0c2015-01-19 11:33:47 +010092#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
Stefan Roeseff7ad172015-12-10 15:02:38 +010093#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roese1a16a0c2015-01-19 11:33:47 +010094
Stefan Roese9b1e2312014-10-22 12:13:19 +020095#endif /* _CONFIG_DB_MV7846MP_GP_H */