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wdenk4ca32362004-12-16 15:52:40 +00001/*
Detlev Zundel69064962009-03-30 00:31:35 +02002 * (C) Copyright 2009
3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
4 *
wdenk8d5d28a2005-04-02 22:37:54 +00005 * (C) Copyright 2003-2005
wdenk4ca32362004-12-16 15:52:40 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk4ca32362004-12-16 15:52:40 +00009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
Masahiro Yamada608ed2c2014-01-16 11:03:07 +090019#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
20#define CONFIG_INKA4X0 1 /* INKA4x0 board */
Anatolij Gustschin70524192015-08-14 07:01:15 +020021#define CONFIG_DISPLAY_BOARDINFO
wdenk4ca32362004-12-16 15:52:40 +000022
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020023/*
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
25 * 0xFFE00000 boot low
26 * 0x00100000 boot from RAM (for testing only)
27 */
28#ifndef CONFIG_SYS_TEXT_BASE
29#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
30#endif
Wolfgang Denk341e5e72010-11-28 21:18:58 +010031#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020032
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk4ca32362004-12-16 15:52:40 +000034
wdenk99408ba2005-02-24 22:44:16 +000035#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
36
Becky Bruce03ea1be2008-05-08 19:02:12 -050037#define CONFIG_HIGH_BATS 1 /* High BATs supported */
38
wdenk4ca32362004-12-16 15:52:40 +000039/*
40 * Serial console configuration
41 */
wdenk99408ba2005-02-24 22:44:16 +000042#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
43#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk4ca32362004-12-16 15:52:40 +000045
46/*
wdenk81414462005-01-31 22:09:11 +000047 * PCI Mapping:
48 * 0x40000000 - 0x4fffffff - PCI Memory
49 * 0x50000000 - 0x50ffffff - PCI IO Space
50 */
51#define CONFIG_PCI 1
52#define CONFIG_PCI_PNP 1
53#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liew521f97b2008-03-30 01:19:06 -050054#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenk81414462005-01-31 22:09:11 +000055
56#define CONFIG_PCI_MEM_BUS 0x40000000
57#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
58#define CONFIG_PCI_MEM_SIZE 0x10000000
59
60#define CONFIG_PCI_IO_BUS 0x50000000
61#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
62#define CONFIG_PCI_IO_SIZE 0x01000000
63
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_XLB_PIPELINING 1
wdenk81414462005-01-31 22:09:11 +000065
66/* Partitions */
67#define CONFIG_MAC_PARTITION
68#define CONFIG_DOS_PARTITION
69#define CONFIG_ISO_PARTITION
70
71/*
Jon Loeliger140b69c2007-07-10 09:38:02 -050072 * BOOTP options
73 */
74#define CONFIG_BOOTP_BOOTFILESIZE
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_GATEWAY
77#define CONFIG_BOOTP_HOSTNAME
78
Jon Loeliger140b69c2007-07-10 09:38:02 -050079/*
Jon Loeliger860435b2007-07-04 22:32:32 -050080 * Command line configuration.
wdenk4ca32362004-12-16 15:52:40 +000081 */
Detlev Zundel69064962009-03-30 00:31:35 +020082#define CONFIG_CMD_DATE
Jon Loeliger860435b2007-07-04 22:32:32 -050083#define CONFIG_CMD_IDE
Jon Loeliger860435b2007-07-04 22:32:32 -050084#define CONFIG_CMD_PCI
Jon Loeliger860435b2007-07-04 22:32:32 -050085
wdenk286dca82005-03-04 11:27:31 +000086#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
87
Wolfgang Denk0708bc62010-10-07 21:51:12 +020088#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089# define CONFIG_SYS_LOWBOOT 1
wdenk4ca32362004-12-16 15:52:40 +000090#endif
91
92/*
93 * Autobooting
94 */
wdenk4ca32362004-12-16 15:52:40 +000095
96#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010097 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk4ca32362004-12-16 15:52:40 +000098 "echo"
99
100#undef CONFIG_BOOTARGS
101
Wolfgang Denka71cec72006-02-07 15:18:25 +0100102#define CONFIG_IPADDR 192.168.100.2
103#define CONFIG_SERVERIP 192.168.100.1
104#define CONFIG_NETMASK 255.255.255.0
105#define HOSTNAME inka4x0
Joe Hershbergere4da2482011-10-13 13:03:48 +0000106#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage"
Joe Hershberger257ff782011-10-13 13:03:47 +0000107#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Wolfgang Denka71cec72006-02-07 15:18:25 +0100108
wdenk4ca32362004-12-16 15:52:40 +0000109#define CONFIG_EXTRA_ENV_SETTINGS \
110 "netdev=eth0\0" \
111 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100112 "nfsroot=${serverip}:${rootpath}\0" \
wdenk4ca32362004-12-16 15:52:40 +0000113 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100114 "addip=setenv bootargs ${bootargs} " \
115 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
116 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denka71cec72006-02-07 15:18:25 +0100117 "addcons=setenv bootargs ${bootargs} " \
118 "console=ttyS0,${baudrate}\0" \
119 "flash_nfs=run nfsargs addip addcons;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100120 "bootm ${kernel_addr}\0" \
Wolfgang Denka71cec72006-02-07 15:18:25 +0100121 "net_nfs=tftp 200000 ${bootfile};" \
122 "run nfsargs addip addcons;bootm\0" \
123 "enable_disp=mw.l 100000 04000000 1;" \
124 "cp.l 100000 f0000b20 1;" \
125 "cp.l 100000 f0000b28 1\0" \
126 "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
127 "ide_boot=ext2load ide 0:1 200000 uImage;" \
Marian Balakowicz8cfe7a82007-11-15 13:24:43 +0100128 "run ideargs addip addcons enable_disp;bootm\0" \
Wolfgang Denka71cec72006-02-07 15:18:25 +0100129 "brightness=255\0" \
wdenk4ca32362004-12-16 15:52:40 +0000130 ""
131
Wolfgang Denka71cec72006-02-07 15:18:25 +0100132#define CONFIG_BOOTCOMMAND "run ide_boot"
wdenk4ca32362004-12-16 15:52:40 +0000133
134/*
135 * IPB Bus clocking configuration.
136 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenk4ca32362004-12-16 15:52:40 +0000138
139/*
140 * Flash configuration
141 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200143#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_BASE 0xffe00000
145#define CONFIG_SYS_FLASH_SIZE 0x00200000
146#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
147#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
148#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
149#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
wdenk4ca32362004-12-16 15:52:40 +0000150
151/*
152 * Environment settings
153 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200154#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200156#define CONFIG_ENV_SIZE 0x2000
157#define CONFIG_ENV_SECT_SIZE 0x2000
wdenk4ca32362004-12-16 15:52:40 +0000158#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk4ca32362004-12-16 15:52:40 +0000160
161/*
162 * Memory map
163 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_MBAR 0xF0000000
165#define CONFIG_SYS_SDRAM_BASE 0x00000000
166#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenk4ca32362004-12-16 15:52:40 +0000167
Marian Balakowicz209d5132007-11-15 13:29:55 +0100168/*
169 * SDRAM controller configuration
170 */
171#undef CONFIG_SDR_MT48LC16M16A2
172#undef CONFIG_DDR_MT46V16M16
173#undef CONFIG_DDR_MT46V32M16
174#undef CONFIG_DDR_HYB25D512160BF
175#define CONFIG_DDR_K4H511638C
wdenk4ca32362004-12-16 15:52:40 +0000176
177/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Michael Zaidmanf969a682010-09-20 08:51:53 +0200179
wdenk4ca32362004-12-16 15:52:40 +0000180/* preserve space for the post_word at end of on-chip SRAM */
Michael Zaidmanf969a682010-09-20 08:51:53 +0200181#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
182
183#ifdef CONFIG_POST
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200184#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
wdenk4ca32362004-12-16 15:52:40 +0000185#else
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200186#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
wdenk4ca32362004-12-16 15:52:40 +0000187#endif
188
Wolfgang Denk0191e472010-10-26 14:34:52 +0200189#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk4ca32362004-12-16 15:52:40 +0000191
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
194# define CONFIG_SYS_RAMBOOT 1
wdenk4ca32362004-12-16 15:52:40 +0000195#endif
196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
198#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
199#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk4ca32362004-12-16 15:52:40 +0000200
201/*
202 * Ethernet configuration
203 */
204#define CONFIG_MPC5xxx_FEC 1
Ben Warrenbc1b9172009-02-05 23:58:25 -0800205#define CONFIG_MPC5xxx_FEC_MII100
wdenk4ca32362004-12-16 15:52:40 +0000206/*
Ben Warrenbc1b9172009-02-05 23:58:25 -0800207 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
wdenk4ca32362004-12-16 15:52:40 +0000208 */
Ben Warrenbc1b9172009-02-05 23:58:25 -0800209/* #define CONFIG_MPC5xxx_FEC_MII10 */
wdenk4ca32362004-12-16 15:52:40 +0000210#define CONFIG_PHY_ADDR 0x00
Wolfgang Denka71cec72006-02-07 15:18:25 +0100211#define CONFIG_MII
wdenk4ca32362004-12-16 15:52:40 +0000212
213/*
214 * GPIO configuration
215 *
wdenk8c61fe52005-04-22 15:09:09 +0000216 * use CS1 as gpio_wkup_6 output
217 * Bit 0 (mask: 0x80000000): 0
wdenk4ca32362004-12-16 15:52:40 +0000218 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
219 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
220 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
221 * EEPROM
222 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
Detlev Zundel69064962009-03-30 00:31:35 +0200223 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
224 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
225 * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
wdenk4ca32362004-12-16 15:52:40 +0000226 */
Detlev Zundel69064962009-03-30 00:31:35 +0200227#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
wdenk4ca32362004-12-16 15:52:40 +0000228
229/*
230 * RTC configuration
231 */
Detlev Zundel69064962009-03-30 00:31:35 +0200232#define CONFIG_RTC_RTC4543 1 /* use external RTC */
233
234/*
235 * Software (bit-bang) three wire serial configuration
236 *
237 * Note that we need the ifdefs because otherwise compilation of
238 * mkimage.c fails.
239 */
240#define CONFIG_SOFT_TWS 1
241
242#ifdef TWS_IMPLEMENTATION
243#include <mpc5xxx.h>
244#include <asm/io.h>
245
246#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
247#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
248#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
249#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
250
251static inline void tws_ce(unsigned bit)
252{
253 struct mpc5xxx_wu_gpio *wu_gpio =
254 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
255 if (bit)
256 setbits_8(&wu_gpio->dvo, TWS_CE);
257 else
258 clrbits_8(&wu_gpio->dvo, TWS_CE);
259}
260
261static inline void tws_wr(unsigned bit)
262{
263 struct mpc5xxx_wu_gpio *wu_gpio =
264 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
265 if (bit)
266 setbits_8(&wu_gpio->dvo, TWS_WR);
267 else
268 clrbits_8(&wu_gpio->dvo, TWS_WR);
269}
270
271static inline void tws_clk(unsigned bit)
272{
273 struct mpc5xxx_gpio *gpio =
274 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
275 if (bit)
276 setbits_8(&gpio->sint_dvo, TWS_CLK);
277 else
278 clrbits_8(&gpio->sint_dvo, TWS_CLK);
279}
280
281static inline void tws_data(unsigned bit)
282{
283 struct mpc5xxx_gpio *gpio =
284 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
285 if (bit)
286 setbits_8(&gpio->sint_dvo, TWS_DATA);
287 else
288 clrbits_8(&gpio->sint_dvo, TWS_DATA);
289}
290
291static inline unsigned tws_data_read(void)
292{
293 struct mpc5xxx_gpio *gpio =
294 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
295 return !!(in_8(&gpio->sint_ival) & TWS_DATA);
296}
297
298static inline void tws_data_config_output(unsigned output)
299{
300 struct mpc5xxx_gpio *gpio =
301 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
302 if (output)
303 setbits_8(&gpio->sint_ddr, TWS_DATA);
304 else
305 clrbits_8(&gpio->sint_ddr, TWS_DATA);
306}
307#endif /* TWS_IMPLEMENTATION */
wdenk4ca32362004-12-16 15:52:40 +0000308
309/*
310 * Miscellaneous configurable options
311 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger860435b2007-07-04 22:32:32 -0500313#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk4ca32362004-12-16 15:52:40 +0000315#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200316#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk4ca32362004-12-16 15:52:40 +0000317#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200318#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
319#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
320#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk4ca32362004-12-16 15:52:40 +0000321
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200322#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger860435b2007-07-04 22:32:32 -0500323#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200324# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger860435b2007-07-04 22:32:32 -0500325#endif
326
wdenk4ca32362004-12-16 15:52:40 +0000327/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200328#define CONFIG_SYS_ALT_MEMTEST
wdenk4ca32362004-12-16 15:52:40 +0000329
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
331#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk4ca32362004-12-16 15:52:40 +0000332
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200333#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk4ca32362004-12-16 15:52:40 +0000334
wdenk4ca32362004-12-16 15:52:40 +0000335/*
wdenk4ca32362004-12-16 15:52:40 +0000336 * Various low-level settings
337 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200338#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
339#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk4ca32362004-12-16 15:52:40 +0000340
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
342#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
343#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
344#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
345#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenk4ca32362004-12-16 15:52:40 +0000346
wdenk62fea7e2005-02-27 23:46:58 +0000347/* 32Mbit SRAM @0x30000000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200348#define CONFIG_SYS_CS1_START 0x30000000
349#define CONFIG_SYS_CS1_SIZE 0x00400000
350#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
wdenk62fea7e2005-02-27 23:46:58 +0000351
352/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_CS2_START 0x80000000
354#define CONFIG_SYS_CS2_SIZE 0x0001000
355#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
wdenk62fea7e2005-02-27 23:46:58 +0000356
wdenkb995b0f2005-03-06 01:21:30 +0000357/* GPIO in @0x30400000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200358#define CONFIG_SYS_CS3_START 0x30400000
359#define CONFIG_SYS_CS3_SIZE 0x00100000
360#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
wdenkb995b0f2005-03-06 01:21:30 +0000361
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200362#define CONFIG_SYS_CS_BURST 0x00000000
363#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenk4ca32362004-12-16 15:52:40 +0000364
wdenk81414462005-01-31 22:09:11 +0000365/*-----------------------------------------------------------------------
366 * USB stuff
367 *-----------------------------------------------------------------------
368 */
369#define CONFIG_USB_OHCI
wdenk99408ba2005-02-24 22:44:16 +0000370#define CONFIG_USB_CLOCK 0x00015555
371#define CONFIG_USB_CONFIG 0x00001000
wdenk81414462005-01-31 22:09:11 +0000372
wdenk286dca82005-03-04 11:27:31 +0000373/*-----------------------------------------------------------------------
374 * IDE/ATA stuff Supports IDE harddisk
375 *-----------------------------------------------------------------------
376 */
377
378#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
379
380#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
381#undef CONFIG_IDE_LED /* LED for ide not supported */
382
wdenk286dca82005-03-04 11:27:31 +0000383#define CONFIG_IDE_PREINIT
384
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200385#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
386#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
wdenk286dca82005-03-04 11:27:31 +0000387
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200388#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
389#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
390#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
391#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
392#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
393#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
wdenk286dca82005-03-04 11:27:31 +0000394
395#define CONFIG_ATAPI 1
Wolfgang Denkf67ef1e2005-09-21 10:07:56 +0200396
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200397#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
wdenk286dca82005-03-04 11:27:31 +0000398
wdenk4ca32362004-12-16 15:52:40 +0000399#endif /* __CONFIG_H */