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Shengzhou Liu49912402014-11-24 17:11:56 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 RDB board configuration file
9 */
10
11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
14/* High Level Configuration Options */
Shengzhou Liu49912402014-11-24 17:11:56 +080015#define CONFIG_DISPLAY_BOARDINFO
16#define CONFIG_BOOKE
17#define CONFIG_E500 /* BOOKE e500 family */
18#define CONFIG_E500MC /* BOOKE e500mc family */
19#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20#define CONFIG_MP /* support multiple processors */
Shengzhou Liu49912402014-11-24 17:11:56 +080021#define CONFIG_ENABLE_36BIT_PHYS
22
23#ifdef CONFIG_PHYS_64BIT
24#define CONFIG_ADDR_MAP 1
25#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
26#endif
27
28#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
29#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
30#define CONFIG_FSL_IFC /* Enable IFC Support */
31
32#define CONFIG_FSL_LAW /* Use common FSL init code */
33#define CONFIG_ENV_OVERWRITE
34
Aneesh Bansal962021a2016-01-22 16:37:22 +053035#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
36
Shengzhou Liu49912402014-11-24 17:11:56 +080037/* support deep sleep */
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080038#ifdef CONFIG_PPC_T1024
Shengzhou Liu49912402014-11-24 17:11:56 +080039#define CONFIG_DEEP_SLEEP
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080040#endif
tang yuantian8dc02f32014-12-17 15:42:54 +080041#if defined(CONFIG_DEEP_SLEEP)
Shengzhou Liu49912402014-11-24 17:11:56 +080042#define CONFIG_SILENT_CONSOLE
tang yuantian8dc02f32014-12-17 15:42:54 +080043#define CONFIG_BOARD_EARLY_INIT_F
44#endif
Shengzhou Liu49912402014-11-24 17:11:56 +080045
46#ifdef CONFIG_RAMBOOT_PBL
47#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080048#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +080049#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080050#elif defined(CONFIG_T1023RDB)
51#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
52#endif
Shengzhou Liu49912402014-11-24 17:11:56 +080053#define CONFIG_SPL_FLUSH_IMAGE
54#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Shengzhou Liu49912402014-11-24 17:11:56 +080055#define CONFIG_FSL_LAW /* Use common FSL init code */
tang yuantian8dc02f32014-12-17 15:42:54 +080056#define CONFIG_SYS_TEXT_BASE 0x30001000
Shengzhou Liu49912402014-11-24 17:11:56 +080057#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
58#define CONFIG_SPL_PAD_TO 0x40000
59#define CONFIG_SPL_MAX_SIZE 0x28000
60#define RESET_VECTOR_OFFSET 0x27FFC
61#define BOOT_PAGE_OFFSET 0x27000
62#ifdef CONFIG_SPL_BUILD
63#define CONFIG_SPL_SKIP_RELOCATE
64#define CONFIG_SPL_COMMON_INIT_DDR
65#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
66#define CONFIG_SYS_NO_FLASH
67#endif
68
69#ifdef CONFIG_NAND
Shengzhou Liu49912402014-11-24 17:11:56 +080070#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
tang yuantian8dc02f32014-12-17 15:42:54 +080071#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
72#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
Shengzhou Liu49912402014-11-24 17:11:56 +080073#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
74#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
75#define CONFIG_SPL_NAND_BOOT
76#endif
77
78#ifdef CONFIG_SPIFLASH
tang yuantian8dc02f32014-12-17 15:42:54 +080079#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu49912402014-11-24 17:11:56 +080080#define CONFIG_SPL_SPI_FLASH_MINIMAL
81#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
tang yuantian8dc02f32014-12-17 15:42:54 +080082#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
83#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
Shengzhou Liu49912402014-11-24 17:11:56 +080084#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
85#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
86#ifndef CONFIG_SPL_BUILD
87#define CONFIG_SYS_MPC85XX_NO_RESETVEC
88#endif
89#define CONFIG_SPL_SPI_BOOT
90#endif
91
92#ifdef CONFIG_SDCARD
tang yuantian8dc02f32014-12-17 15:42:54 +080093#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu49912402014-11-24 17:11:56 +080094#define CONFIG_SPL_MMC_MINIMAL
95#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
tang yuantian8dc02f32014-12-17 15:42:54 +080096#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
97#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
Shengzhou Liu49912402014-11-24 17:11:56 +080098#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
99#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
100#ifndef CONFIG_SPL_BUILD
101#define CONFIG_SYS_MPC85XX_NO_RESETVEC
102#endif
103#define CONFIG_SPL_MMC_BOOT
104#endif
105
106#endif /* CONFIG_RAMBOOT_PBL */
107
108#ifndef CONFIG_SYS_TEXT_BASE
109#define CONFIG_SYS_TEXT_BASE 0xeff40000
110#endif
111
112#ifndef CONFIG_RESET_VECTOR_ADDRESS
113#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
114#endif
115
116#ifndef CONFIG_SYS_NO_FLASH
117#define CONFIG_FLASH_CFI_DRIVER
118#define CONFIG_SYS_FLASH_CFI
119#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
120#endif
121
122/* PCIe Boot - Master */
123#define CONFIG_SRIO_PCIE_BOOT_MASTER
124/*
125 * for slave u-boot IMAGE instored in master memory space,
126 * PHYS must be aligned based on the SIZE
127 */
128#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
129#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
130#ifdef CONFIG_PHYS_64BIT
131#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
132#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
133#else
134#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
135#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
136#endif
137/*
138 * for slave UCODE and ENV instored in master memory space,
139 * PHYS must be aligned based on the SIZE
140 */
141#ifdef CONFIG_PHYS_64BIT
142#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
143#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
144#else
145#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
146#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
147#endif
148#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
149/* slave core release by master*/
150#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
151#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
152
153/* PCIe Boot - Slave */
154#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
155#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
156#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
158/* Set 1M boot space for PCIe boot */
159#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
160#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
161 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
162#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
163#define CONFIG_SYS_NO_FLASH
164#endif
165
166#if defined(CONFIG_SPIFLASH)
167#define CONFIG_SYS_EXTRA_ENV_RELOC
168#define CONFIG_ENV_IS_IN_SPI_FLASH
169#define CONFIG_ENV_SPI_BUS 0
170#define CONFIG_ENV_SPI_CS 0
171#define CONFIG_ENV_SPI_MAX_HZ 10000000
172#define CONFIG_ENV_SPI_MODE 0
173#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
174#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800175#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800176#define CONFIG_ENV_SECT_SIZE 0x10000
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800177#elif defined(CONFIG_T1023RDB)
178#define CONFIG_ENV_SECT_SIZE 0x40000
179#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800180#elif defined(CONFIG_SDCARD)
181#define CONFIG_SYS_EXTRA_ENV_RELOC
182#define CONFIG_ENV_IS_IN_MMC
183#define CONFIG_SYS_MMC_ENV_DEV 0
184#define CONFIG_ENV_SIZE 0x2000
185#define CONFIG_ENV_OFFSET (512 * 0x800)
186#elif defined(CONFIG_NAND)
187#define CONFIG_SYS_EXTRA_ENV_RELOC
188#define CONFIG_ENV_IS_IN_NAND
189#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800190#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800191#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800192#elif defined(CONFIG_T1023RDB)
193#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
194#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800195#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
196#define CONFIG_ENV_IS_IN_REMOTE
197#define CONFIG_ENV_ADDR 0xffe20000
198#define CONFIG_ENV_SIZE 0x2000
199#elif defined(CONFIG_ENV_IS_NOWHERE)
200#define CONFIG_ENV_SIZE 0x2000
201#else
202#define CONFIG_ENV_IS_IN_FLASH
203#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
204#define CONFIG_ENV_SIZE 0x2000
205#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
206#endif
207
Shengzhou Liu49912402014-11-24 17:11:56 +0800208#ifndef __ASSEMBLY__
209unsigned long get_board_sys_clk(void);
210unsigned long get_board_ddr_clk(void);
211#endif
212
213#define CONFIG_SYS_CLK_FREQ 100000000
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800214#define CONFIG_DDR_CLK_FREQ 100000000
Shengzhou Liu49912402014-11-24 17:11:56 +0800215
216/*
217 * These can be toggled for performance analysis, otherwise use default.
218 */
219#define CONFIG_SYS_CACHE_STASHING
220#define CONFIG_BACKSIDE_L2_CACHE
221#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
222#define CONFIG_BTB /* toggle branch predition */
223#define CONFIG_DDR_ECC
224#ifdef CONFIG_DDR_ECC
225#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
226#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
227#endif
228
229#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
230#define CONFIG_SYS_MEMTEST_END 0x00400000
231#define CONFIG_SYS_ALT_MEMTEST
232#define CONFIG_PANIC_HANG /* do not reset board on panic */
233
234/*
235 * Config the L3 Cache as L3 SRAM
236 */
237#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
238#define CONFIG_SYS_L3_SIZE (256 << 10)
239#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
240#ifdef CONFIG_RAMBOOT_PBL
241#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
242#endif
243#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
244#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
245#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
246#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
247
248#ifdef CONFIG_PHYS_64BIT
249#define CONFIG_SYS_DCSRBAR 0xf0000000
250#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
251#endif
252
253/* EEPROM */
254#define CONFIG_ID_EEPROM
255#define CONFIG_SYS_I2C_EEPROM_NXID
256#define CONFIG_SYS_EEPROM_BUS_NUM 0
257#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
258#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
259#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
260#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
261
262/*
263 * DDR Setup
264 */
265#define CONFIG_VERY_BIG_RAM
266#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
267#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
268#define CONFIG_DIMM_SLOTS_PER_CTLR 1
269#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800270#define CONFIG_FSL_DDR_INTERACTIVE
271#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800272#define CONFIG_DDR_SPD
273#define CONFIG_SYS_FSL_DDR3
Shengzhou Liu49912402014-11-24 17:11:56 +0800274#define CONFIG_SYS_SPD_BUS_NUM 0
275#define SPD_EEPROM_ADDRESS 0x51
Shengzhou Liu49912402014-11-24 17:11:56 +0800276#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800277#elif defined(CONFIG_T1023RDB)
278#define CONFIG_SYS_FSL_DDR4
279#define CONFIG_SYS_DDR_RAW_TIMING
280#define CONFIG_SYS_SDRAM_SIZE 2048
281#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800282
283/*
284 * IFC Definitions
285 */
286#define CONFIG_SYS_FLASH_BASE 0xe8000000
287#ifdef CONFIG_PHYS_64BIT
288#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
289#else
290#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
291#endif
292
293#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
294#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
295 CSPR_PORT_SIZE_16 | \
296 CSPR_MSEL_NOR | \
297 CSPR_V)
298#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
299
300/* NOR Flash Timing Params */
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800301#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800302#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800303#elif defined(CONFIG_T1023RDB)
Shengzhou Liu0a197892015-06-17 16:37:01 +0800304#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800305 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
306#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800307#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
308 FTIM0_NOR_TEADC(0x5) | \
309 FTIM0_NOR_TEAHC(0x5))
310#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
311 FTIM1_NOR_TRAD_NOR(0x1A) |\
312 FTIM1_NOR_TSEQRAD_NOR(0x13))
313#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
314 FTIM2_NOR_TCH(0x4) | \
315 FTIM2_NOR_TWPH(0x0E) | \
316 FTIM2_NOR_TWP(0x1c))
317#define CONFIG_SYS_NOR_FTIM3 0x0
318
319#define CONFIG_SYS_FLASH_QUIET_TEST
320#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
321
322#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
323#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
324#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
325#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
326
327#define CONFIG_SYS_FLASH_EMPTY_INFO
328#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
329
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800330#ifdef CONFIG_T1024RDB
Shengzhou Liu49912402014-11-24 17:11:56 +0800331/* CPLD on IFC */
332#define CONFIG_SYS_CPLD_BASE 0xffdf0000
333#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
334#define CONFIG_SYS_CSPR2_EXT (0xf)
335#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
336 | CSPR_PORT_SIZE_8 \
337 | CSPR_MSEL_GPCM \
338 | CSPR_V)
339#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
340#define CONFIG_SYS_CSOR2 0x0
341
342/* CPLD Timing parameters for IFC CS2 */
343#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
344 FTIM0_GPCM_TEADC(0x0e) | \
345 FTIM0_GPCM_TEAHC(0x0e))
346#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
347 FTIM1_GPCM_TRAD(0x1f))
348#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
349 FTIM2_GPCM_TCH(0x8) | \
350 FTIM2_GPCM_TWP(0x1f))
351#define CONFIG_SYS_CS2_FTIM3 0x0
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800352#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800353
354/* NAND Flash on IFC */
355#define CONFIG_NAND_FSL_IFC
356#define CONFIG_SYS_NAND_BASE 0xff800000
357#ifdef CONFIG_PHYS_64BIT
358#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
359#else
360#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
361#endif
362#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
363#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
364 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
365 | CSPR_MSEL_NAND /* MSEL = NAND */ \
366 | CSPR_V)
367#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
368
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800369#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800370#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
371 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
372 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
373 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
374 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
375 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
376 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800377#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
378#elif defined(CONFIG_T1023RDB)
Jaiprakash Singhc4e609f2015-05-22 15:21:07 +0530379#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
380 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
381 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800382 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
383 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
384 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
385 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
386#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
387#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800388
389#define CONFIG_SYS_NAND_ONFI_DETECTION
Shengzhou Liu49912402014-11-24 17:11:56 +0800390/* ONFI NAND Flash mode0 Timing Params */
391#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
392 FTIM0_NAND_TWP(0x18) | \
393 FTIM0_NAND_TWCHT(0x07) | \
394 FTIM0_NAND_TWH(0x0a))
395#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
396 FTIM1_NAND_TWBE(0x39) | \
397 FTIM1_NAND_TRR(0x0e) | \
398 FTIM1_NAND_TRP(0x18))
399#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
400 FTIM2_NAND_TREH(0x0a) | \
401 FTIM2_NAND_TWHRE(0x1e))
402#define CONFIG_SYS_NAND_FTIM3 0x0
403
404#define CONFIG_SYS_NAND_DDR_LAW 11
405#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
406#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu49912402014-11-24 17:11:56 +0800407#define CONFIG_CMD_NAND
408
Shengzhou Liu49912402014-11-24 17:11:56 +0800409#if defined(CONFIG_NAND)
410#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
411#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
412#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
413#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
414#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
415#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
416#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
417#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
418#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
419#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
420#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
421#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
422#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
423#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
424#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
425#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
426#else
427#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
428#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
429#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
430#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
431#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
432#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
433#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
434#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
435#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
436#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
437#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
438#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
439#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
440#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
441#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
442#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
443#endif
444
445#ifdef CONFIG_SPL_BUILD
446#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
447#else
448#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
449#endif
450
451#if defined(CONFIG_RAMBOOT_PBL)
452#define CONFIG_SYS_RAMBOOT
453#endif
454
455#define CONFIG_BOARD_EARLY_INIT_R
456#define CONFIG_MISC_INIT_R
457
458#define CONFIG_HWCONFIG
459
460/* define to use L1 as initial stack */
461#define CONFIG_L1_INIT_RAM
462#define CONFIG_SYS_INIT_RAM_LOCK
463#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
464#ifdef CONFIG_PHYS_64BIT
465#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunee7b4832015-08-17 13:31:51 -0700466#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu49912402014-11-24 17:11:56 +0800467/* The assembler doesn't like typecast */
468#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
469 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
470 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
471#else
York Sunee7b4832015-08-17 13:31:51 -0700472#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liu49912402014-11-24 17:11:56 +0800473#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
474#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
475#endif
476#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
477
478#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
479 GENERATED_GBL_DATA_SIZE)
480#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
481
482#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
483#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
484
485/* Serial Port */
486#define CONFIG_CONS_INDEX 1
Shengzhou Liu49912402014-11-24 17:11:56 +0800487#define CONFIG_SYS_NS16550_SERIAL
488#define CONFIG_SYS_NS16550_REG_SIZE 1
489#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
490
491#define CONFIG_SYS_BAUDRATE_TABLE \
492 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
493
494#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
495#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
496#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
497#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
498#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
499
Shengzhou Liu49912402014-11-24 17:11:56 +0800500/* Video */
501#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
502#ifdef CONFIG_FSL_DIU_FB
503#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
504#define CONFIG_VIDEO
505#define CONFIG_CMD_BMP
506#define CONFIG_CFB_CONSOLE
507#define CONFIG_VIDEO_SW_CURSOR
508#define CONFIG_VGA_AS_SINGLE_DEVICE
509#define CONFIG_VIDEO_LOGO
510#define CONFIG_VIDEO_BMP_LOGO
511#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
512/*
513 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
514 * disable empty flash sector detection, which is I/O-intensive.
515 */
516#undef CONFIG_SYS_FLASH_EMPTY_INFO
517#endif
518
Shengzhou Liu49912402014-11-24 17:11:56 +0800519/* I2C */
520#define CONFIG_SYS_I2C
521#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
522#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
523#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
524#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
525#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
526#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
527#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
528
Shengzhou Liu0a197892015-06-17 16:37:01 +0800529#define I2C_PCA6408_BUS_NUM 1
530#define I2C_PCA6408_ADDR 0x20
Shengzhou Liu49912402014-11-24 17:11:56 +0800531
532/* I2C bus multiplexer */
533#define I2C_MUX_CH_DEFAULT 0x8
534
535/*
536 * RTC configuration
537 */
538#define RTC
539#define CONFIG_RTC_DS1337 1
540#define CONFIG_SYS_I2C_RTC_ADDR 0x68
541
542/*
543 * eSPI - Enhanced SPI
544 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800545#define CONFIG_SPI_FLASH_BAR
546#define CONFIG_SF_DEFAULT_SPEED 10000000
547#define CONFIG_SF_DEFAULT_MODE 0
548
549/*
550 * General PCIe
551 * Memory space is mapped 1-1, but I/O space must start from 0.
552 */
553#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400554#define CONFIG_PCIE1 /* PCIE controller 1 */
555#define CONFIG_PCIE2 /* PCIE controller 2 */
556#define CONFIG_PCIE3 /* PCIE controller 3 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800557#ifdef CONFIG_PPC_T1040
Robert P. J. Daya8099812016-05-03 19:52:49 -0400558#define CONFIG_PCIE4 /* PCIE controller 4 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800559#endif
560#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
561#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
562#define CONFIG_PCI_INDIRECT_BRIDGE
563
564#ifdef CONFIG_PCI
565/* controller 1, direct to uli, tgtid 3, Base address 20000 */
566#ifdef CONFIG_PCIE1
567#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
568#ifdef CONFIG_PHYS_64BIT
569#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
570#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
571#else
572#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
573#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
574#endif
575#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
576#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
577#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
578#ifdef CONFIG_PHYS_64BIT
579#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
580#else
581#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
582#endif
583#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
584#endif
585
586/* controller 2, Slot 2, tgtid 2, Base address 201000 */
587#ifdef CONFIG_PCIE2
588#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
589#ifdef CONFIG_PHYS_64BIT
590#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
591#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
592#else
593#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
594#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
595#endif
596#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
597#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
598#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
599#ifdef CONFIG_PHYS_64BIT
600#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
601#else
602#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
603#endif
604#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
605#endif
606
607/* controller 3, Slot 1, tgtid 1, Base address 202000 */
608#ifdef CONFIG_PCIE3
609#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
610#ifdef CONFIG_PHYS_64BIT
611#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
612#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
613#else
614#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
615#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
616#endif
617#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
618#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
619#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
620#ifdef CONFIG_PHYS_64BIT
621#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
622#else
623#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
624#endif
625#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
626#endif
627
628/* controller 4, Base address 203000, to be removed */
629#ifdef CONFIG_PCIE4
630#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
631#ifdef CONFIG_PHYS_64BIT
632#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
633#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
634#else
635#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
636#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
637#endif
638#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
639#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
640#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
641#ifdef CONFIG_PHYS_64BIT
642#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
643#else
644#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
645#endif
646#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
647#endif
648
649#define CONFIG_PCI_PNP /* do pci plug-and-play */
Shengzhou Liu49912402014-11-24 17:11:56 +0800650#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
651#define CONFIG_DOS_PARTITION
652#endif /* CONFIG_PCI */
653
654/*
655 * USB
656 */
657#define CONFIG_HAS_FSL_DR_USB
658
659#ifdef CONFIG_HAS_FSL_DR_USB
660#define CONFIG_USB_EHCI
Shengzhou Liu49912402014-11-24 17:11:56 +0800661#define CONFIG_USB_EHCI_FSL
662#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liu49912402014-11-24 17:11:56 +0800663#endif
664
665/*
666 * SDHC
667 */
668#define CONFIG_MMC
669#ifdef CONFIG_MMC
670#define CONFIG_FSL_ESDHC
671#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Shengzhou Liu49912402014-11-24 17:11:56 +0800672#define CONFIG_GENERIC_MMC
Shengzhou Liu49912402014-11-24 17:11:56 +0800673#define CONFIG_DOS_PARTITION
674#endif
675
676/* Qman/Bman */
677#ifndef CONFIG_NOBQFMAN
678#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceurf9c39742014-12-03 18:08:43 -0500679#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liu49912402014-11-24 17:11:56 +0800680#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
681#ifdef CONFIG_PHYS_64BIT
682#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
683#else
684#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
685#endif
686#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500687#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
688#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
689#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
690#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
691#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
692 CONFIG_SYS_BMAN_CENA_SIZE)
693#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
694#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceurf9c39742014-12-03 18:08:43 -0500695#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liu49912402014-11-24 17:11:56 +0800696#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
697#ifdef CONFIG_PHYS_64BIT
698#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
699#else
700#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
701#endif
702#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500703#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
704#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
705#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
706#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
707#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
708 CONFIG_SYS_QMAN_CENA_SIZE)
709#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
710#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu49912402014-11-24 17:11:56 +0800711
712#define CONFIG_SYS_DPAA_FMAN
713
Shengzhou Liu0a197892015-06-17 16:37:01 +0800714#ifdef CONFIG_T1024RDB
Shengzhou Liu49912402014-11-24 17:11:56 +0800715#define CONFIG_QE
716#define CONFIG_U_QE
Shengzhou Liu0a197892015-06-17 16:37:01 +0800717#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800718/* Default address of microcode for the Linux FMan driver */
719#if defined(CONFIG_SPIFLASH)
720/*
721 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
722 * env, so we got 0x110000.
723 */
724#define CONFIG_SYS_QE_FW_IN_SPIFLASH
725#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
726#define CONFIG_SYS_QE_FW_ADDR 0x130000
727#elif defined(CONFIG_SDCARD)
728/*
729 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
730 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
731 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
732 */
733#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
734#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
735#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
736#elif defined(CONFIG_NAND)
737#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800738#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800739#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
740#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800741#elif defined(CONFIG_T1023RDB)
742#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
743#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
744#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800745#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
746/*
747 * Slave has no ucode locally, it can fetch this from remote. When implementing
748 * in two corenet boards, slave's ucode could be stored in master's memory
749 * space, the address can be mapped from slave TLB->slave LAW->
750 * slave SRIO or PCIE outbound window->master inbound window->
751 * master LAW->the ucode address in master's memory space.
752 */
753#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
754#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
755#else
756#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
757#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
758#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
759#endif
760#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
761#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
762#endif /* CONFIG_NOBQFMAN */
763
764#ifdef CONFIG_SYS_DPAA_FMAN
765#define CONFIG_FMAN_ENET
766#define CONFIG_PHYLIB_10G
767#define CONFIG_PHY_REALTEK
Shengzhou Liuccc57ef2014-12-17 16:51:08 +0800768#define CONFIG_PHY_AQUANTIA
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800769#if defined(CONFIG_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800770#define RGMII_PHY1_ADDR 0x2
771#define RGMII_PHY2_ADDR 0x6
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800772#define SGMII_AQR_PHY_ADDR 0x2
Shengzhou Liu49912402014-11-24 17:11:56 +0800773#define FM1_10GEC1_PHY_ADDR 0x1
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800774#elif defined(CONFIG_T1023RDB)
775#define RGMII_PHY1_ADDR 0x1
776#define SGMII_RTK_PHY_ADDR 0x3
777#define SGMII_AQR_PHY_ADDR 0x2
778#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800779#endif
780
781#ifdef CONFIG_FMAN_ENET
782#define CONFIG_MII /* MII PHY management */
783#define CONFIG_ETHPRIME "FM1@DTSEC4"
784#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
785#endif
786
787/*
788 * Dynamic MTD Partition support with mtdparts
789 */
790#ifndef CONFIG_SYS_NO_FLASH
791#define CONFIG_MTD_DEVICE
792#define CONFIG_MTD_PARTITIONS
793#define CONFIG_CMD_MTDPARTS
794#define CONFIG_FLASH_CFI_MTD
795#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
796 "spi0=spife110000.1"
797#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
798 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
799 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
800 "1m(uboot),5m(kernel),128k(dtb),-(user)"
801#endif
802
803/*
804 * Environment
805 */
806#define CONFIG_LOADS_ECHO /* echo on for serial download */
807#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
808
809/*
810 * Command line configuration.
811 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800812#define CONFIG_CMD_DATE
Shengzhou Liu49912402014-11-24 17:11:56 +0800813#define CONFIG_CMD_EEPROM
Shengzhou Liu49912402014-11-24 17:11:56 +0800814#define CONFIG_CMD_ERRATA
Shengzhou Liu49912402014-11-24 17:11:56 +0800815#define CONFIG_CMD_IRQ
Shengzhou Liu49912402014-11-24 17:11:56 +0800816#define CONFIG_CMD_REGINFO
Shengzhou Liu49912402014-11-24 17:11:56 +0800817
818#ifdef CONFIG_PCI
819#define CONFIG_CMD_PCI
Shengzhou Liu49912402014-11-24 17:11:56 +0800820#endif
821
822/*
823 * Miscellaneous configurable options
824 */
825#define CONFIG_SYS_LONGHELP /* undef to save memory */
826#define CONFIG_CMDLINE_EDITING /* Command-line editing */
827#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
828#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu49912402014-11-24 17:11:56 +0800829#ifdef CONFIG_CMD_KGDB
830#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
831#else
832#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
833#endif
834#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
835#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
836#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
837
838/*
839 * For booting Linux, the board info and command line data
840 * have to be in the first 64 MB of memory, since this is
841 * the maximum mapped by the Linux kernel during initialization.
842 */
843#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
844#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
845
846#ifdef CONFIG_CMD_KGDB
847#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
848#endif
849
850/*
851 * Environment Configuration
852 */
853#define CONFIG_ROOTPATH "/opt/nfsroot"
854#define CONFIG_BOOTFILE "uImage"
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800855#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Shengzhou Liu49912402014-11-24 17:11:56 +0800856#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
Shengzhou Liu49912402014-11-24 17:11:56 +0800857#define CONFIG_BAUDRATE 115200
858#define __USB_PHY_TYPE utmi
859
860#ifdef CONFIG_PPC_T1024
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800861#define CONFIG_BOARDNAME t1024rdb
862#define BANK_INTLV cs0_cs1
Shengzhou Liu49912402014-11-24 17:11:56 +0800863#else
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800864#define CONFIG_BOARDNAME t1023rdb
865#define BANK_INTLV null
Shengzhou Liu49912402014-11-24 17:11:56 +0800866#endif
867
868#define CONFIG_EXTRA_ENV_SETTINGS \
869 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800870 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
Shengzhou Liu49912402014-11-24 17:11:56 +0800871 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
872 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
873 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
874 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
875 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
876 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
877 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
878 "netdev=eth0\0" \
879 "tftpflash=tftpboot $loadaddr $uboot && " \
880 "protect off $ubootaddr +$filesize && " \
881 "erase $ubootaddr +$filesize && " \
882 "cp.b $loadaddr $ubootaddr $filesize && " \
883 "protect on $ubootaddr +$filesize && " \
884 "cmp.b $loadaddr $ubootaddr $filesize\0" \
885 "consoledev=ttyS0\0" \
886 "ramdiskaddr=2000000\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500887 "fdtaddr=1e00000\0" \
Shengzhou Liu49912402014-11-24 17:11:56 +0800888 "bdev=sda3\0"
889
890#define CONFIG_LINUX \
891 "setenv bootargs root=/dev/ram rw " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "setenv ramdiskaddr 0x02000000;" \
894 "setenv fdtaddr 0x00c00000;" \
895 "setenv loadaddr 0x1000000;" \
896 "bootm $loadaddr $ramdiskaddr $fdtaddr"
897
Shengzhou Liu49912402014-11-24 17:11:56 +0800898#define CONFIG_NFSBOOTCOMMAND \
899 "setenv bootargs root=/dev/nfs rw " \
900 "nfsroot=$serverip:$rootpath " \
901 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
902 "console=$consoledev,$baudrate $othbootargs;" \
903 "tftp $loadaddr $bootfile;" \
904 "tftp $fdtaddr $fdtfile;" \
905 "bootm $loadaddr - $fdtaddr"
906
907#define CONFIG_BOOTCOMMAND CONFIG_LINUX
908
Aneesh Bansal962021a2016-01-22 16:37:22 +0530909/* Hash command with SHA acceleration supported in hardware */
910#ifdef CONFIG_FSL_CAAM
911#define CONFIG_CMD_HASH
912#define CONFIG_SHA_HW_ACCEL
913#endif
914
Shengzhou Liu49912402014-11-24 17:11:56 +0800915#include <asm/fsl_secure_boot.h>
Aneesh Bansal962021a2016-01-22 16:37:22 +0530916
Shengzhou Liu49912402014-11-24 17:11:56 +0800917#endif /* __T1024RDB_H */