blob: 92c69e5cf25f4b25189f38f53c84348b6bf60d85 [file] [log] [blame]
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00005 */
6
7/*
8 * BSC9131 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
harninder rai604b3ca2014-12-02 15:55:47 +053014#define CONFIG_DISPLAY_BOARDINFO
15
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000016#ifdef CONFIG_BSC9131RDB
17#define CONFIG_BSC9131
18#define CONFIG_NAND_FSL_IFC
19#endif
20
21#ifdef CONFIG_SPIFLASH
22#define CONFIG_RAMBOOT_SPIFLASH
23#define CONFIG_SYS_RAMBOOT
24#define CONFIG_SYS_EXTRA_ENV_RELOC
25#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053026#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000027#endif
28
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053029#ifdef CONFIG_NAND
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053030#define CONFIG_SPL_INIT_MINIMAL
Prabhakar Kushwahaafffcb02013-12-11 12:42:11 +053031#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053032#define CONFIG_SPL_FLUSH_IMAGE
33#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34
35#define CONFIG_SYS_TEXT_BASE 0x00201000
36#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
37#define CONFIG_SPL_MAX_SIZE 8192
38#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
39#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053040#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053041#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
42#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
43#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
44#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000045#endif
46
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053047#ifdef CONFIG_SPL_BUILD
48#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
49#else
50#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
51#endif
52
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000053/* High Level Configuration Options */
54#define CONFIG_BOOKE /* BOOKE */
55#define CONFIG_E500 /* BOOKE e500 family */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000056#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta12af67f2014-10-15 11:35:31 +053057#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000058
59#define CONFIG_FSL_LAW /* Use common FSL init code */
60#define CONFIG_TSEC_ENET
61#define CONFIG_ENV_OVERWRITE
62
63#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
Priyanka Jainf9146bd2013-04-01 12:12:45 +053064#if defined(CONFIG_SYS_CLK_100)
65#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
66#else
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000067#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
Priyanka Jainf9146bd2013-04-01 12:12:45 +053068#endif
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000069
70#define CONFIG_HWCONFIG
71/*
72 * These can be toggled for performance analysis, otherwise use default.
73 */
74#define CONFIG_L2_CACHE /* toggle L2 cache */
75#define CONFIG_BTB /* enable branch predition */
76
77#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
78#define CONFIG_SYS_MEMTEST_END 0x01ffffff
79
80/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -070081#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000082#undef CONFIG_SYS_DDR_RAW_TIMING
83#undef CONFIG_DDR_SPD
84#define CONFIG_SYS_SPD_BUS_NUM 0
85#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
86
87#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
88
89#ifndef __ASSEMBLY__
90extern unsigned long get_sdram_size(void);
91#endif
92#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
93#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
94#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95
96#define CONFIG_NUM_DDR_CONTROLLERS 1
97#define CONFIG_DIMM_SLOTS_PER_CTLR 1
98#define CONFIG_CHIP_SELECTS_PER_CTRL 1
99
100#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
101#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
102#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
103
104#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
105#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
106#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
107#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
108
109#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
110#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
111#define CONFIG_SYS_DDR_RCW_1 0x00000000
112#define CONFIG_SYS_DDR_RCW_2 0x00000000
113#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
114#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
115#define CONFIG_SYS_DDR_TIMING_4 0x00000001
116#define CONFIG_SYS_DDR_TIMING_5 0x02401400
117
118#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
119#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
120#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
121#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
122#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
123#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
124#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
125#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
126#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
127
128/*
129 * Base addresses -- Note these are effective addresses where the
130 * actual resources get mapped (not physical addresses)
131 */
132/* relocated CCSRBAR */
133#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
134#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
135
136#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
137 /* CONFIG_SYS_IMMR */
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530138/* DSP CCSRBAR */
139#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
140#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000141
142/*
143 * Memory map
144 *
145 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
146 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530147 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000148 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
149 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
150 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
151 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530152 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000153 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
154 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
155 *
156 */
157
158/*
159 * IFC Definitions
160 */
161#define CONFIG_SYS_NO_FLASH
162
163/* NAND Flash on IFC */
164#define CONFIG_SYS_NAND_BASE 0xff800000
165#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
166
167#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
168 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
169 | CSPR_MSEL_NAND /* MSEL = NAND */ \
170 | CSPR_V)
171#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
172
173#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
174 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
175 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
176 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
177 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
178 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
179 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
180
181/* NAND Flash Timing Params */
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530182#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
183 | FTIM0_NAND_TWP(0x05) \
184 | FTIM0_NAND_TWCHT(0x02) \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000185 | FTIM0_NAND_TWH(0x04))
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530186#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
187 | FTIM1_NAND_TWBE(0x1E) \
188 | FTIM1_NAND_TRR(0x07) \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000189 | FTIM1_NAND_TRP(0x05))
190#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
191 | FTIM2_NAND_TREH(0x04) \
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530192 | FTIM2_NAND_TWHRE(0x11))
193#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000194
195#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
196#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000197#define CONFIG_CMD_NAND
198#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
199
200#define CONFIG_SYS_NAND_DDR_LAW 11
201
202/* Set up IFC registers for boot location NAND */
203#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
204#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
205#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
206#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
207#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
208#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
209#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
210
211#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
212
213#define CONFIG_SYS_INIT_RAM_LOCK
214#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
York Sun515fbb42016-04-06 13:22:10 -0700215#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000216
York Sun515fbb42016-04-06 13:22:10 -0700217#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000218 - GENERATED_GBL_DATA_SIZE)
219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530221#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000222#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
223
224/* Serial Port */
225#define CONFIG_CONS_INDEX 1
226#undef CONFIG_SERIAL_SOFTWARE_FIFO
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000227#define CONFIG_SYS_NS16550_SERIAL
228#define CONFIG_SYS_NS16550_REG_SIZE 1
229#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530230#ifdef CONFIG_SPL_BUILD
231#define CONFIG_NS16550_MIN_FUNCTIONS
232#endif
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000233
234#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
235
236#define CONFIG_SYS_BAUDRATE_TABLE \
237 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
238
239#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
240
Heiko Schocherf2850742012-10-24 13:48:22 +0200241#define CONFIG_SYS_I2C
242#define CONFIG_SYS_I2C_FSL
243#define CONFIG_SYS_FSL_I2C_SPEED 400000
244#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
245#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000246
247/* I2C EEPROM */
248#define CONFIG_CMD_EEPROM
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000249#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
250#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
251#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
252
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000253/* eSPI - Enhanced SPI */
254#ifdef CONFIG_FSL_ESPI
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000255#define CONFIG_SF_DEFAULT_SPEED 10000000
256#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
257#endif
258
259#if defined(CONFIG_TSEC_ENET)
260
261#define CONFIG_MII /* MII PHY management */
262#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
263#define CONFIG_TSEC1 1
264#define CONFIG_TSEC1_NAME "eTSEC1"
265#define CONFIG_TSEC2 1
266#define CONFIG_TSEC2_NAME "eTSEC2"
267
268#define TSEC1_PHY_ADDR 0
269#define TSEC2_PHY_ADDR 3
270
271#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
272#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
273
274#define TSEC1_PHYIDX 0
275
276#define TSEC2_PHYIDX 0
277
278#define CONFIG_ETHPRIME "eTSEC1"
279
280#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
281
282#endif /* CONFIG_TSEC_ENET */
283
284/*
285 * Environment
286 */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000287#if defined(CONFIG_RAMBOOT_SPIFLASH)
288#define CONFIG_ENV_IS_IN_SPI_FLASH
289#define CONFIG_ENV_SPI_BUS 0
290#define CONFIG_ENV_SPI_CS 0
291#define CONFIG_ENV_SPI_MAX_HZ 10000000
292#define CONFIG_ENV_SPI_MODE 0
293#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
294#define CONFIG_ENV_SECT_SIZE 0x10000
295#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530296#elif defined(CONFIG_NAND)
297#define CONFIG_ENV_IS_IN_NAND
298#define CONFIG_SYS_EXTRA_ENV_RELOC
299#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530300#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530301#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
302#elif defined(CONFIG_SYS_RAMBOOT)
303#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000304#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530305#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000306#endif
307
308#define CONFIG_LOADS_ECHO /* echo on for serial download */
309#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
310
311/*
312 * Command line configuration.
313 */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000314#define CONFIG_CMD_ERRATA
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000315#define CONFIG_CMD_IRQ
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000316#define CONFIG_DOS_PARTITION
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000317#define CONFIG_CMD_REGINFO
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000318
319/*
320 * Miscellaneous configurable options
321 */
322#define CONFIG_SYS_LONGHELP /* undef to save memory */
323#define CONFIG_CMDLINE_EDITING /* Command-line editing */
324#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
325#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000326
327#if defined(CONFIG_CMD_KGDB)
328#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
329#else
330#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
331#endif
332#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
333 /* Print Buffer Size */
334#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
335#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000336
337/*
338 * For booting Linux, the board info and command line data
339 * have to be in the first 64 MB of memory, since this is
340 * the maximum mapped by the Linux kernel during initialization.
341 */
342#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
343#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
344
345#if defined(CONFIG_CMD_KGDB)
346#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000347#endif
348
Ruchika Gupta12af67f2014-10-15 11:35:31 +0530349/* Hash command with SHA acceleration supported in hardware */
350#ifdef CONFIG_FSL_CAAM
351#define CONFIG_CMD_HASH
352#define CONFIG_SHA_HW_ACCEL
353#endif
354
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000355#define CONFIG_USB_EHCI
356
357#ifdef CONFIG_USB_EHCI
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000358#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
359#define CONFIG_USB_EHCI_FSL
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000360#define CONFIG_HAS_FSL_DR_USB
361#endif
362
363/*
Ashish Kumarc4570202014-10-07 18:02:23 +0530364 * Dynamic MTD Partition support with mtdparts
365 */
366#define CONFIG_MTD_DEVICE
367#define CONFIG_MTD_PARTITIONS
368#define CONFIG_CMD_MTDPARTS
369#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
370#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
371 "8m(kernel),512k(dtb),-(fs)"
372/*
373 * Override partitions in device tree using info
374 * in "mtdparts" environment variable
375 */
376#ifdef CONFIG_CMD_MTDPARTS
377#define CONFIG_FDT_FIXUP_PARTITIONS
378#endif
379
380/*
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000381 * Environment Configuration
382 */
383
384#if defined(CONFIG_TSEC_ENET)
385#define CONFIG_HAS_ETH0
386#endif
387
388#define CONFIG_HOSTNAME BSC9131rdb
389#define CONFIG_ROOTPATH "/opt/nfsroot"
390#define CONFIG_BOOTFILE "uImage"
391#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
392
393#define CONFIG_BAUDRATE 115200
394
395#define CONFIG_EXTRA_ENV_SETTINGS \
396 "netdev=eth0\0" \
397 "uboot=" CONFIG_UBOOTPATH "\0" \
398 "loadaddr=1000000\0" \
399 "bootfile=uImage\0" \
400 "consoledev=ttyS0\0" \
401 "ramdiskaddr=2000000\0" \
402 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500403 "fdtaddr=1e00000\0" \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000404 "fdtfile=bsc9131rdb.dtb\0" \
405 "bdev=sda1\0" \
406 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
Priyanka Jain20732df2013-04-04 14:40:32 +0530407 "bootm_size=0x37000000\0" \
408 "othbootargs=ramdisk_size=600000 " \
409 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000410 "usbext2boot=setenv bootargs root=/dev/ram rw " \
411 "console=$consoledev,$baudrate $othbootargs; " \
412 "usb start;" \
413 "ext2load usb 0:4 $loadaddr $bootfile;" \
414 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
415 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
416 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
417
418#define CONFIG_RAMBOOTCOMMAND \
419 "setenv bootargs root=/dev/ram rw " \
420 "console=$consoledev,$baudrate $othbootargs; " \
421 "tftp $ramdiskaddr $ramdiskfile;" \
422 "tftp $loadaddr $bootfile;" \
423 "tftp $fdtaddr $fdtfile;" \
424 "bootm $loadaddr $ramdiskaddr $fdtaddr"
425
426#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
427
428#endif /* __CONFIG_H */