Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 Google, Inc |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0 |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <clk-uclass.h> |
| 9 | #include <dm.h> |
| 10 | #include <errno.h> |
| 11 | #include <syscon.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <asm/arch/clock.h> |
| 14 | #include <asm/arch/cru_rk3399.h> |
| 15 | #include <asm/arch/hardware.h> |
| 16 | #include <dm/lists.h> |
| 17 | #include <dt-bindings/clock/rk3399-cru.h> |
| 18 | |
| 19 | DECLARE_GLOBAL_DATA_PTR; |
| 20 | |
| 21 | struct rk3399_clk_priv { |
| 22 | struct rk3399_cru *cru; |
| 23 | ulong rate; |
| 24 | }; |
| 25 | |
Kever Yang | e54d26a | 2016-08-12 17:47:15 +0800 | [diff] [blame] | 26 | struct rk3399_pmuclk_priv { |
| 27 | struct rk3399_pmucru *pmucru; |
| 28 | }; |
| 29 | |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 30 | struct pll_div { |
| 31 | u32 refdiv; |
| 32 | u32 fbdiv; |
| 33 | u32 postdiv1; |
| 34 | u32 postdiv2; |
| 35 | u32 frac; |
| 36 | }; |
| 37 | |
| 38 | #define RATE_TO_DIV(input_rate, output_rate) \ |
| 39 | ((input_rate) / (output_rate) - 1); |
| 40 | #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
| 41 | |
| 42 | #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ |
| 43 | .refdiv = _refdiv,\ |
| 44 | .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ |
| 45 | .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; |
| 46 | |
| 47 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); |
| 48 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); |
| 49 | static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); |
| 50 | |
| 51 | static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); |
| 52 | static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); |
| 53 | |
| 54 | static const struct pll_div *apll_l_cfgs[] = { |
| 55 | [APLL_L_1600_MHZ] = &apll_l_1600_cfg, |
| 56 | [APLL_L_600_MHZ] = &apll_l_600_cfg, |
| 57 | }; |
| 58 | |
| 59 | enum { |
| 60 | /* PLL_CON0 */ |
| 61 | PLL_FBDIV_MASK = 0xfff, |
| 62 | PLL_FBDIV_SHIFT = 0, |
| 63 | |
| 64 | /* PLL_CON1 */ |
| 65 | PLL_POSTDIV2_SHIFT = 12, |
| 66 | PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, |
| 67 | PLL_POSTDIV1_SHIFT = 8, |
| 68 | PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, |
| 69 | PLL_REFDIV_MASK = 0x3f, |
| 70 | PLL_REFDIV_SHIFT = 0, |
| 71 | |
| 72 | /* PLL_CON2 */ |
| 73 | PLL_LOCK_STATUS_SHIFT = 31, |
| 74 | PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, |
| 75 | PLL_FRACDIV_MASK = 0xffffff, |
| 76 | PLL_FRACDIV_SHIFT = 0, |
| 77 | |
| 78 | /* PLL_CON3 */ |
| 79 | PLL_MODE_SHIFT = 8, |
| 80 | PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, |
| 81 | PLL_MODE_SLOW = 0, |
| 82 | PLL_MODE_NORM, |
| 83 | PLL_MODE_DEEP, |
| 84 | PLL_DSMPD_SHIFT = 3, |
| 85 | PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, |
| 86 | PLL_INTEGER_MODE = 1, |
| 87 | |
| 88 | /* PMUCRU_CLKSEL_CON0 */ |
| 89 | PMU_PCLK_DIV_CON_MASK = 0x1f, |
| 90 | PMU_PCLK_DIV_CON_SHIFT = 0, |
| 91 | |
| 92 | /* PMUCRU_CLKSEL_CON1 */ |
| 93 | SPI3_PLL_SEL_SHIFT = 7, |
| 94 | SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, |
| 95 | SPI3_PLL_SEL_24M = 0, |
| 96 | SPI3_PLL_SEL_PPLL = 1, |
| 97 | SPI3_DIV_CON_SHIFT = 0x0, |
| 98 | SPI3_DIV_CON_MASK = 0x7f, |
| 99 | |
| 100 | /* PMUCRU_CLKSEL_CON2 */ |
| 101 | I2C_DIV_CON_MASK = 0x7f, |
Kever Yang | e54d26a | 2016-08-12 17:47:15 +0800 | [diff] [blame] | 102 | CLK_I2C8_DIV_CON_SHIFT = 8, |
| 103 | CLK_I2C0_DIV_CON_SHIFT = 0, |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 104 | |
| 105 | /* PMUCRU_CLKSEL_CON3 */ |
Kever Yang | e54d26a | 2016-08-12 17:47:15 +0800 | [diff] [blame] | 106 | CLK_I2C4_DIV_CON_SHIFT = 0, |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 107 | |
| 108 | /* CLKSEL_CON0 */ |
| 109 | ACLKM_CORE_L_DIV_CON_SHIFT = 8, |
| 110 | ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT, |
| 111 | CLK_CORE_L_PLL_SEL_SHIFT = 6, |
| 112 | CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT, |
| 113 | CLK_CORE_L_PLL_SEL_ALPLL = 0x0, |
| 114 | CLK_CORE_L_PLL_SEL_ABPLL = 0x1, |
| 115 | CLK_CORE_L_PLL_SEL_DPLL = 0x10, |
| 116 | CLK_CORE_L_PLL_SEL_GPLL = 0x11, |
| 117 | CLK_CORE_L_DIV_MASK = 0x1f, |
| 118 | CLK_CORE_L_DIV_SHIFT = 0, |
| 119 | |
| 120 | /* CLKSEL_CON1 */ |
| 121 | PCLK_DBG_L_DIV_SHIFT = 0x8, |
| 122 | PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT, |
| 123 | ATCLK_CORE_L_DIV_SHIFT = 0, |
| 124 | ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, |
| 125 | |
| 126 | /* CLKSEL_CON14 */ |
| 127 | PCLK_PERIHP_DIV_CON_SHIFT = 12, |
| 128 | PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, |
| 129 | HCLK_PERIHP_DIV_CON_SHIFT = 8, |
| 130 | HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, |
| 131 | ACLK_PERIHP_PLL_SEL_SHIFT = 7, |
| 132 | ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, |
| 133 | ACLK_PERIHP_PLL_SEL_CPLL = 0, |
| 134 | ACLK_PERIHP_PLL_SEL_GPLL = 1, |
| 135 | ACLK_PERIHP_DIV_CON_SHIFT = 0, |
| 136 | ACLK_PERIHP_DIV_CON_MASK = 0x1f, |
| 137 | |
| 138 | /* CLKSEL_CON21 */ |
| 139 | ACLK_EMMC_PLL_SEL_SHIFT = 7, |
| 140 | ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, |
| 141 | ACLK_EMMC_PLL_SEL_GPLL = 0x1, |
| 142 | ACLK_EMMC_DIV_CON_SHIFT = 0, |
| 143 | ACLK_EMMC_DIV_CON_MASK = 0x1f, |
| 144 | |
| 145 | /* CLKSEL_CON22 */ |
| 146 | CLK_EMMC_PLL_SHIFT = 8, |
| 147 | CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, |
| 148 | CLK_EMMC_PLL_SEL_GPLL = 0x1, |
Kever Yang | dc850de | 2016-08-04 11:44:58 +0800 | [diff] [blame] | 149 | CLK_EMMC_PLL_SEL_24M = 0x5, |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 150 | CLK_EMMC_DIV_CON_SHIFT = 0, |
| 151 | CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, |
| 152 | |
| 153 | /* CLKSEL_CON23 */ |
| 154 | PCLK_PERILP0_DIV_CON_SHIFT = 12, |
| 155 | PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, |
| 156 | HCLK_PERILP0_DIV_CON_SHIFT = 8, |
| 157 | HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, |
| 158 | ACLK_PERILP0_PLL_SEL_SHIFT = 7, |
| 159 | ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, |
| 160 | ACLK_PERILP0_PLL_SEL_CPLL = 0, |
| 161 | ACLK_PERILP0_PLL_SEL_GPLL = 1, |
| 162 | ACLK_PERILP0_DIV_CON_SHIFT = 0, |
| 163 | ACLK_PERILP0_DIV_CON_MASK = 0x1f, |
| 164 | |
| 165 | /* CLKSEL_CON25 */ |
| 166 | PCLK_PERILP1_DIV_CON_SHIFT = 8, |
| 167 | PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, |
| 168 | HCLK_PERILP1_PLL_SEL_SHIFT = 7, |
| 169 | HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, |
| 170 | HCLK_PERILP1_PLL_SEL_CPLL = 0, |
| 171 | HCLK_PERILP1_PLL_SEL_GPLL = 1, |
| 172 | HCLK_PERILP1_DIV_CON_SHIFT = 0, |
| 173 | HCLK_PERILP1_DIV_CON_MASK = 0x1f, |
| 174 | |
| 175 | /* CLKSEL_CON26 */ |
| 176 | CLK_SARADC_DIV_CON_SHIFT = 8, |
| 177 | CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT, |
| 178 | |
| 179 | /* CLKSEL_CON27 */ |
| 180 | CLK_TSADC_SEL_X24M = 0x0, |
| 181 | CLK_TSADC_SEL_SHIFT = 15, |
| 182 | CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, |
| 183 | CLK_TSADC_DIV_CON_SHIFT = 0, |
| 184 | CLK_TSADC_DIV_CON_MASK = 0x3ff, |
| 185 | |
| 186 | /* CLKSEL_CON47 & CLKSEL_CON48 */ |
| 187 | ACLK_VOP_PLL_SEL_SHIFT = 6, |
| 188 | ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, |
| 189 | ACLK_VOP_PLL_SEL_CPLL = 0x1, |
| 190 | ACLK_VOP_DIV_CON_SHIFT = 0, |
| 191 | ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, |
| 192 | |
| 193 | /* CLKSEL_CON49 & CLKSEL_CON50 */ |
| 194 | DCLK_VOP_DCLK_SEL_SHIFT = 11, |
| 195 | DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, |
| 196 | DCLK_VOP_DCLK_SEL_DIVOUT = 0, |
| 197 | DCLK_VOP_PLL_SEL_SHIFT = 8, |
| 198 | DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, |
| 199 | DCLK_VOP_PLL_SEL_VPLL = 0, |
| 200 | DCLK_VOP_DIV_CON_MASK = 0xff, |
| 201 | DCLK_VOP_DIV_CON_SHIFT = 0, |
| 202 | |
| 203 | /* CLKSEL_CON58 */ |
| 204 | CLK_SPI_PLL_SEL_MASK = 1, |
| 205 | CLK_SPI_PLL_SEL_CPLL = 0, |
| 206 | CLK_SPI_PLL_SEL_GPLL = 1, |
| 207 | CLK_SPI_PLL_DIV_CON_MASK = 0x7f, |
| 208 | CLK_SPI5_PLL_DIV_CON_SHIFT = 8, |
| 209 | CLK_SPI5_PLL_SEL_SHIFT = 15, |
| 210 | |
| 211 | /* CLKSEL_CON59 */ |
| 212 | CLK_SPI1_PLL_SEL_SHIFT = 15, |
| 213 | CLK_SPI1_PLL_DIV_CON_SHIFT = 8, |
| 214 | CLK_SPI0_PLL_SEL_SHIFT = 7, |
| 215 | CLK_SPI0_PLL_DIV_CON_SHIFT = 0, |
| 216 | |
| 217 | /* CLKSEL_CON60 */ |
| 218 | CLK_SPI4_PLL_SEL_SHIFT = 15, |
| 219 | CLK_SPI4_PLL_DIV_CON_SHIFT = 8, |
| 220 | CLK_SPI2_PLL_SEL_SHIFT = 7, |
| 221 | CLK_SPI2_PLL_DIV_CON_SHIFT = 0, |
| 222 | |
| 223 | /* CLKSEL_CON61 */ |
| 224 | CLK_I2C_PLL_SEL_MASK = 1, |
| 225 | CLK_I2C_PLL_SEL_CPLL = 0, |
| 226 | CLK_I2C_PLL_SEL_GPLL = 1, |
| 227 | CLK_I2C5_PLL_SEL_SHIFT = 15, |
| 228 | CLK_I2C5_DIV_CON_SHIFT = 8, |
| 229 | CLK_I2C1_PLL_SEL_SHIFT = 7, |
| 230 | CLK_I2C1_DIV_CON_SHIFT = 0, |
| 231 | |
| 232 | /* CLKSEL_CON62 */ |
| 233 | CLK_I2C6_PLL_SEL_SHIFT = 15, |
| 234 | CLK_I2C6_DIV_CON_SHIFT = 8, |
| 235 | CLK_I2C2_PLL_SEL_SHIFT = 7, |
| 236 | CLK_I2C2_DIV_CON_SHIFT = 0, |
| 237 | |
| 238 | /* CLKSEL_CON63 */ |
| 239 | CLK_I2C7_PLL_SEL_SHIFT = 15, |
| 240 | CLK_I2C7_DIV_CON_SHIFT = 8, |
| 241 | CLK_I2C3_PLL_SEL_SHIFT = 7, |
| 242 | CLK_I2C3_DIV_CON_SHIFT = 0, |
| 243 | |
| 244 | /* CRU_SOFTRST_CON4 */ |
| 245 | RESETN_DDR0_REQ_SHIFT = 8, |
| 246 | RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, |
| 247 | RESETN_DDRPHY0_REQ_SHIFT = 9, |
| 248 | RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, |
| 249 | RESETN_DDR1_REQ_SHIFT = 12, |
| 250 | RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, |
| 251 | RESETN_DDRPHY1_REQ_SHIFT = 13, |
| 252 | RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, |
| 253 | }; |
| 254 | |
| 255 | #define VCO_MAX_KHZ (3200 * (MHz / KHz)) |
| 256 | #define VCO_MIN_KHZ (800 * (MHz / KHz)) |
| 257 | #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) |
| 258 | #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) |
| 259 | |
| 260 | /* |
| 261 | * the div restructions of pll in integer mode, these are defined in |
| 262 | * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 |
| 263 | */ |
| 264 | #define PLL_DIV_MIN 16 |
| 265 | #define PLL_DIV_MAX 3200 |
| 266 | |
| 267 | /* |
| 268 | * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): |
| 269 | * Formulas also embedded within the Fractional PLL Verilog model: |
| 270 | * If DSMPD = 1 (DSM is disabled, "integer mode") |
| 271 | * FOUTVCO = FREF / REFDIV * FBDIV |
| 272 | * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 |
| 273 | * Where: |
| 274 | * FOUTVCO = Fractional PLL non-divided output frequency |
| 275 | * FOUTPOSTDIV = Fractional PLL divided output frequency |
| 276 | * (output of second post divider) |
| 277 | * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) |
| 278 | * REFDIV = Fractional PLL input reference clock divider |
| 279 | * FBDIV = Integer value programmed into feedback divide |
| 280 | * |
| 281 | */ |
| 282 | static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) |
| 283 | { |
| 284 | /* All 8 PLLs have same VCO and output frequency range restrictions. */ |
| 285 | u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; |
| 286 | u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; |
| 287 | |
| 288 | debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " |
| 289 | "postdiv2=%d, vco=%u khz, output=%u khz\n", |
| 290 | pll_con, div->fbdiv, div->refdiv, div->postdiv1, |
| 291 | div->postdiv2, vco_khz, output_khz); |
| 292 | assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && |
| 293 | output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && |
| 294 | div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); |
| 295 | |
| 296 | /* |
| 297 | * When power on or changing PLL setting, |
| 298 | * we must force PLL into slow mode to ensure output stable clock. |
| 299 | */ |
| 300 | rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, |
| 301 | PLL_MODE_SLOW << PLL_MODE_SHIFT); |
| 302 | |
| 303 | /* use integer mode */ |
| 304 | rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, |
| 305 | PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); |
| 306 | |
| 307 | rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, |
| 308 | div->fbdiv << PLL_FBDIV_SHIFT); |
| 309 | rk_clrsetreg(&pll_con[1], |
| 310 | PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | |
| 311 | PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, |
| 312 | (div->postdiv2 << PLL_POSTDIV2_SHIFT) | |
| 313 | (div->postdiv1 << PLL_POSTDIV1_SHIFT) | |
| 314 | (div->refdiv << PLL_REFDIV_SHIFT)); |
| 315 | |
| 316 | /* waiting for pll lock */ |
| 317 | while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) |
| 318 | udelay(1); |
| 319 | |
| 320 | /* pll enter normal mode */ |
| 321 | rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, |
| 322 | PLL_MODE_NORM << PLL_MODE_SHIFT); |
| 323 | } |
| 324 | |
| 325 | static int pll_para_config(u32 freq_hz, struct pll_div *div) |
| 326 | { |
| 327 | u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; |
| 328 | u32 postdiv1, postdiv2 = 1; |
| 329 | u32 fref_khz; |
| 330 | u32 diff_khz, best_diff_khz; |
| 331 | const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; |
| 332 | const u32 max_postdiv1 = 7, max_postdiv2 = 7; |
| 333 | u32 vco_khz; |
| 334 | u32 freq_khz = freq_hz / KHz; |
| 335 | |
| 336 | if (!freq_hz) { |
| 337 | printf("%s: the frequency can't be 0 Hz\n", __func__); |
| 338 | return -1; |
| 339 | } |
| 340 | |
| 341 | postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); |
| 342 | if (postdiv1 > max_postdiv1) { |
| 343 | postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); |
| 344 | postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); |
| 345 | } |
| 346 | |
| 347 | vco_khz = freq_khz * postdiv1 * postdiv2; |
| 348 | |
| 349 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || |
| 350 | postdiv2 > max_postdiv2) { |
| 351 | printf("%s: Cannot find out a supported VCO" |
| 352 | " for Frequency (%uHz).\n", __func__, freq_hz); |
| 353 | return -1; |
| 354 | } |
| 355 | |
| 356 | div->postdiv1 = postdiv1; |
| 357 | div->postdiv2 = postdiv2; |
| 358 | |
| 359 | best_diff_khz = vco_khz; |
| 360 | for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { |
| 361 | fref_khz = ref_khz / refdiv; |
| 362 | |
| 363 | fbdiv = vco_khz / fref_khz; |
| 364 | if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) |
| 365 | continue; |
| 366 | diff_khz = vco_khz - fbdiv * fref_khz; |
| 367 | if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { |
| 368 | fbdiv++; |
| 369 | diff_khz = fref_khz - diff_khz; |
| 370 | } |
| 371 | |
| 372 | if (diff_khz >= best_diff_khz) |
| 373 | continue; |
| 374 | |
| 375 | best_diff_khz = diff_khz; |
| 376 | div->refdiv = refdiv; |
| 377 | div->fbdiv = fbdiv; |
| 378 | } |
| 379 | |
| 380 | if (best_diff_khz > 4 * (MHz/KHz)) { |
| 381 | printf("%s: Failed to match output frequency %u, " |
| 382 | "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, |
| 383 | best_diff_khz * KHz); |
| 384 | return -1; |
| 385 | } |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static void rkclk_init(struct rk3399_cru *cru) |
| 390 | { |
| 391 | u32 aclk_div; |
| 392 | u32 hclk_div; |
| 393 | u32 pclk_div; |
| 394 | |
| 395 | /* |
| 396 | * some cru registers changed by bootrom, we'd better reset them to |
| 397 | * reset/default values described in TRM to avoid confusion in kernel. |
| 398 | * Please consider these three lines as a fix of bootrom bug. |
| 399 | */ |
| 400 | rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); |
| 401 | rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); |
| 402 | rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); |
| 403 | |
| 404 | /* configure gpll cpll */ |
| 405 | rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); |
| 406 | rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); |
| 407 | |
| 408 | /* configure perihp aclk, hclk, pclk */ |
| 409 | aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; |
| 410 | assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
| 411 | |
| 412 | hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; |
| 413 | assert((hclk_div + 1) * PERIHP_HCLK_HZ == |
| 414 | PERIHP_ACLK_HZ && (hclk_div < 0x4)); |
| 415 | |
| 416 | pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; |
| 417 | assert((pclk_div + 1) * PERIHP_PCLK_HZ == |
| 418 | PERIHP_ACLK_HZ && (pclk_div < 0x7)); |
| 419 | |
| 420 | rk_clrsetreg(&cru->clksel_con[14], |
| 421 | PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | |
| 422 | ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, |
| 423 | pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | |
| 424 | hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | |
| 425 | ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | |
| 426 | aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); |
| 427 | |
| 428 | /* configure perilp0 aclk, hclk, pclk */ |
| 429 | aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; |
| 430 | assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
| 431 | |
| 432 | hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; |
| 433 | assert((hclk_div + 1) * PERILP0_HCLK_HZ == |
| 434 | PERILP0_ACLK_HZ && (hclk_div < 0x4)); |
| 435 | |
| 436 | pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; |
| 437 | assert((pclk_div + 1) * PERILP0_PCLK_HZ == |
| 438 | PERILP0_ACLK_HZ && (pclk_div < 0x7)); |
| 439 | |
| 440 | rk_clrsetreg(&cru->clksel_con[23], |
| 441 | PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | |
| 442 | ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, |
| 443 | pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | |
| 444 | hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | |
| 445 | ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | |
| 446 | aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); |
| 447 | |
| 448 | /* perilp1 hclk select gpll as source */ |
| 449 | hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; |
| 450 | assert((hclk_div + 1) * PERILP1_HCLK_HZ == |
| 451 | GPLL_HZ && (hclk_div < 0x1f)); |
| 452 | |
| 453 | pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; |
| 454 | assert((pclk_div + 1) * PERILP1_HCLK_HZ == |
| 455 | PERILP1_HCLK_HZ && (hclk_div < 0x7)); |
| 456 | |
| 457 | rk_clrsetreg(&cru->clksel_con[25], |
| 458 | PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | |
| 459 | HCLK_PERILP1_PLL_SEL_MASK, |
| 460 | pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | |
| 461 | hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | |
| 462 | HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); |
| 463 | } |
| 464 | |
| 465 | void rk3399_configure_cpu(struct rk3399_cru *cru, |
| 466 | enum apll_l_frequencies apll_l_freq) |
| 467 | { |
| 468 | u32 aclkm_div; |
| 469 | u32 pclk_dbg_div; |
| 470 | u32 atclk_div; |
| 471 | |
| 472 | rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); |
| 473 | |
| 474 | aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; |
| 475 | assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && |
| 476 | aclkm_div < 0x1f); |
| 477 | |
| 478 | pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; |
| 479 | assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && |
| 480 | pclk_dbg_div < 0x1f); |
| 481 | |
| 482 | atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; |
| 483 | assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && |
| 484 | atclk_div < 0x1f); |
| 485 | |
| 486 | rk_clrsetreg(&cru->clksel_con[0], |
| 487 | ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK | |
| 488 | CLK_CORE_L_DIV_MASK, |
| 489 | aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT | |
| 490 | CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT | |
| 491 | 0 << CLK_CORE_L_DIV_SHIFT); |
| 492 | |
| 493 | rk_clrsetreg(&cru->clksel_con[1], |
| 494 | PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK, |
| 495 | pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | |
| 496 | atclk_div << ATCLK_CORE_L_DIV_SHIFT); |
| 497 | } |
| 498 | #define I2C_CLK_REG_MASK(bus) \ |
| 499 | (I2C_DIV_CON_MASK << \ |
| 500 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 501 | CLK_I2C_PLL_SEL_MASK << \ |
| 502 | CLK_I2C ##bus## _PLL_SEL_SHIFT) |
| 503 | |
| 504 | #define I2C_CLK_REG_VALUE(bus, clk_div) \ |
| 505 | ((clk_div - 1) << \ |
| 506 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 507 | CLK_I2C_PLL_SEL_GPLL << \ |
| 508 | CLK_I2C ##bus## _PLL_SEL_SHIFT) |
| 509 | |
| 510 | #define I2C_CLK_DIV_VALUE(con, bus) \ |
| 511 | (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ |
| 512 | I2C_DIV_CON_MASK; |
| 513 | |
Kever Yang | e54d26a | 2016-08-12 17:47:15 +0800 | [diff] [blame] | 514 | #define I2C_PMUCLK_REG_MASK(bus) \ |
| 515 | (I2C_DIV_CON_MASK << \ |
| 516 | CLK_I2C ##bus## _DIV_CON_SHIFT) |
| 517 | |
| 518 | #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ |
| 519 | ((clk_div - 1) << \ |
| 520 | CLK_I2C ##bus## _DIV_CON_SHIFT) |
| 521 | |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 522 | static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) |
| 523 | { |
| 524 | u32 div, con; |
| 525 | |
| 526 | switch (clk_id) { |
| 527 | case SCLK_I2C1: |
| 528 | con = readl(&cru->clksel_con[61]); |
| 529 | div = I2C_CLK_DIV_VALUE(con, 1); |
| 530 | break; |
| 531 | case SCLK_I2C2: |
| 532 | con = readl(&cru->clksel_con[62]); |
| 533 | div = I2C_CLK_DIV_VALUE(con, 2); |
| 534 | break; |
| 535 | case SCLK_I2C3: |
| 536 | con = readl(&cru->clksel_con[63]); |
| 537 | div = I2C_CLK_DIV_VALUE(con, 3); |
| 538 | break; |
| 539 | case SCLK_I2C5: |
| 540 | con = readl(&cru->clksel_con[61]); |
| 541 | div = I2C_CLK_DIV_VALUE(con, 5); |
| 542 | break; |
| 543 | case SCLK_I2C6: |
| 544 | con = readl(&cru->clksel_con[62]); |
| 545 | div = I2C_CLK_DIV_VALUE(con, 6); |
| 546 | break; |
| 547 | case SCLK_I2C7: |
| 548 | con = readl(&cru->clksel_con[63]); |
| 549 | div = I2C_CLK_DIV_VALUE(con, 7); |
| 550 | break; |
| 551 | default: |
| 552 | printf("do not support this i2c bus\n"); |
| 553 | return -EINVAL; |
| 554 | } |
| 555 | |
| 556 | return DIV_TO_RATE(GPLL_HZ, div); |
| 557 | } |
| 558 | |
| 559 | static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) |
| 560 | { |
| 561 | int src_clk_div; |
| 562 | |
| 563 | /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ |
| 564 | src_clk_div = GPLL_HZ / hz; |
| 565 | assert(src_clk_div - 1 < 127); |
| 566 | |
| 567 | switch (clk_id) { |
| 568 | case SCLK_I2C1: |
| 569 | rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), |
| 570 | I2C_CLK_REG_VALUE(1, src_clk_div)); |
| 571 | break; |
| 572 | case SCLK_I2C2: |
| 573 | rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), |
| 574 | I2C_CLK_REG_VALUE(2, src_clk_div)); |
| 575 | break; |
| 576 | case SCLK_I2C3: |
| 577 | rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), |
| 578 | I2C_CLK_REG_VALUE(3, src_clk_div)); |
| 579 | break; |
| 580 | case SCLK_I2C5: |
| 581 | rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), |
| 582 | I2C_CLK_REG_VALUE(5, src_clk_div)); |
| 583 | break; |
| 584 | case SCLK_I2C6: |
| 585 | rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), |
| 586 | I2C_CLK_REG_VALUE(6, src_clk_div)); |
| 587 | break; |
| 588 | case SCLK_I2C7: |
| 589 | rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), |
| 590 | I2C_CLK_REG_VALUE(7, src_clk_div)); |
| 591 | break; |
| 592 | default: |
| 593 | printf("do not support this i2c bus\n"); |
| 594 | return -EINVAL; |
| 595 | } |
| 596 | |
| 597 | return DIV_TO_RATE(GPLL_HZ, src_clk_div); |
| 598 | } |
| 599 | |
| 600 | static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) |
| 601 | { |
| 602 | struct pll_div vpll_config = {0}; |
| 603 | int aclk_vop = 198*MHz; |
| 604 | void *aclkreg_addr, *dclkreg_addr; |
| 605 | u32 div; |
| 606 | |
| 607 | switch (clk_id) { |
| 608 | case DCLK_VOP0: |
| 609 | aclkreg_addr = &cru->clksel_con[47]; |
| 610 | dclkreg_addr = &cru->clksel_con[49]; |
| 611 | break; |
| 612 | case DCLK_VOP1: |
| 613 | aclkreg_addr = &cru->clksel_con[48]; |
| 614 | dclkreg_addr = &cru->clksel_con[50]; |
| 615 | break; |
| 616 | default: |
| 617 | return -EINVAL; |
| 618 | } |
| 619 | /* vop aclk source clk: cpll */ |
| 620 | div = CPLL_HZ / aclk_vop; |
| 621 | assert(div - 1 < 32); |
| 622 | |
| 623 | rk_clrsetreg(aclkreg_addr, |
| 624 | ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, |
| 625 | ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | |
| 626 | (div - 1) << ACLK_VOP_DIV_CON_SHIFT); |
| 627 | |
| 628 | /* vop dclk source from vpll, and equals to vpll(means div == 1) */ |
| 629 | if (pll_para_config(hz, &vpll_config)) |
| 630 | return -1; |
| 631 | |
| 632 | rkclk_set_pll(&cru->vpll_con[0], &vpll_config); |
| 633 | |
| 634 | rk_clrsetreg(dclkreg_addr, |
| 635 | DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| |
| 636 | DCLK_VOP_DIV_CON_MASK, |
| 637 | DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | |
| 638 | DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | |
| 639 | (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); |
| 640 | |
| 641 | return hz; |
| 642 | } |
| 643 | |
| 644 | static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) |
| 645 | { |
| 646 | u32 div, con; |
| 647 | |
| 648 | switch (clk_id) { |
| 649 | case SCLK_SDMMC: |
| 650 | con = readl(&cru->clksel_con[16]); |
| 651 | break; |
| 652 | case SCLK_EMMC: |
| 653 | con = readl(&cru->clksel_con[21]); |
| 654 | break; |
| 655 | default: |
| 656 | return -EINVAL; |
| 657 | } |
Kever Yang | dc850de | 2016-08-04 11:44:58 +0800 | [diff] [blame] | 658 | div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 659 | |
Kever Yang | dc850de | 2016-08-04 11:44:58 +0800 | [diff] [blame] | 660 | if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT |
| 661 | == CLK_EMMC_PLL_SEL_24M) |
| 662 | return DIV_TO_RATE(24*1024*1024, div); |
| 663 | else |
| 664 | return DIV_TO_RATE(GPLL_HZ, div); |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, |
| 668 | ulong clk_id, ulong set_rate) |
| 669 | { |
| 670 | int src_clk_div; |
| 671 | int aclk_emmc = 198*MHz; |
| 672 | |
| 673 | switch (clk_id) { |
| 674 | case SCLK_SDMMC: |
Kever Yang | dc850de | 2016-08-04 11:44:58 +0800 | [diff] [blame] | 675 | /* Select clk_sdmmc source from GPLL by default */ |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 676 | src_clk_div = GPLL_HZ / set_rate; |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 677 | |
Kever Yang | dc850de | 2016-08-04 11:44:58 +0800 | [diff] [blame] | 678 | if (src_clk_div > 127) { |
| 679 | /* use 24MHz source for 400KHz clock */ |
| 680 | src_clk_div = 24*1024*1024 / set_rate; |
| 681 | rk_clrsetreg(&cru->clksel_con[16], |
| 682 | CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, |
| 683 | CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | |
| 684 | (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); |
| 685 | } else { |
| 686 | rk_clrsetreg(&cru->clksel_con[16], |
| 687 | CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, |
| 688 | CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | |
| 689 | (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); |
| 690 | } |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 691 | break; |
| 692 | case SCLK_EMMC: |
| 693 | /* Select aclk_emmc source from GPLL */ |
| 694 | src_clk_div = GPLL_HZ / aclk_emmc; |
| 695 | assert(src_clk_div - 1 < 31); |
| 696 | |
| 697 | rk_clrsetreg(&cru->clksel_con[21], |
| 698 | ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, |
| 699 | ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | |
| 700 | (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); |
| 701 | |
| 702 | /* Select clk_emmc source from GPLL too */ |
| 703 | src_clk_div = GPLL_HZ / set_rate; |
| 704 | assert(src_clk_div - 1 < 127); |
| 705 | |
| 706 | rk_clrsetreg(&cru->clksel_con[22], |
| 707 | CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, |
| 708 | CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | |
| 709 | (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); |
| 710 | break; |
| 711 | default: |
| 712 | return -EINVAL; |
| 713 | } |
| 714 | return rk3399_mmc_get_clk(cru, clk_id); |
| 715 | } |
| 716 | |
| 717 | static ulong rk3399_clk_get_rate(struct clk *clk) |
| 718 | { |
| 719 | struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); |
| 720 | ulong rate = 0; |
| 721 | |
| 722 | switch (clk->id) { |
| 723 | case 0 ... 63: |
| 724 | return 0; |
| 725 | case SCLK_SDMMC: |
| 726 | case SCLK_EMMC: |
| 727 | rate = rk3399_mmc_get_clk(priv->cru, clk->id); |
| 728 | break; |
| 729 | case SCLK_I2C1: |
| 730 | case SCLK_I2C2: |
| 731 | case SCLK_I2C3: |
| 732 | case SCLK_I2C5: |
| 733 | case SCLK_I2C6: |
| 734 | case SCLK_I2C7: |
| 735 | rate = rk3399_i2c_get_clk(priv->cru, clk->id); |
| 736 | break; |
| 737 | case DCLK_VOP0: |
| 738 | case DCLK_VOP1: |
| 739 | break; |
| 740 | default: |
| 741 | return -ENOENT; |
| 742 | } |
| 743 | |
| 744 | return rate; |
| 745 | } |
| 746 | |
| 747 | static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) |
| 748 | { |
| 749 | struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); |
| 750 | ulong ret = 0; |
| 751 | |
| 752 | switch (clk->id) { |
| 753 | case 0 ... 63: |
| 754 | return 0; |
| 755 | case SCLK_SDMMC: |
| 756 | case SCLK_EMMC: |
| 757 | ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); |
| 758 | break; |
| 759 | case SCLK_I2C1: |
| 760 | case SCLK_I2C2: |
| 761 | case SCLK_I2C3: |
| 762 | case SCLK_I2C5: |
| 763 | case SCLK_I2C6: |
| 764 | case SCLK_I2C7: |
| 765 | ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); |
| 766 | break; |
| 767 | case DCLK_VOP0: |
| 768 | case DCLK_VOP1: |
Kever Yang | e54d26a | 2016-08-12 17:47:15 +0800 | [diff] [blame] | 769 | ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); |
Kever Yang | ca19eac | 2016-07-29 10:35:25 +0800 | [diff] [blame] | 770 | break; |
| 771 | default: |
| 772 | return -ENOENT; |
| 773 | } |
| 774 | |
| 775 | return ret; |
| 776 | } |
| 777 | |
| 778 | static struct clk_ops rk3399_clk_ops = { |
| 779 | .get_rate = rk3399_clk_get_rate, |
| 780 | .set_rate = rk3399_clk_set_rate, |
| 781 | }; |
| 782 | |
| 783 | void *rockchip_get_cru(void) |
| 784 | { |
| 785 | struct udevice *dev; |
| 786 | fdt_addr_t *addr; |
| 787 | int ret; |
| 788 | |
| 789 | ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3399", &dev); |
| 790 | if (ret) |
| 791 | return ERR_PTR(ret); |
| 792 | |
| 793 | addr = dev_get_addr_ptr(dev); |
| 794 | if ((fdt_addr_t)addr == FDT_ADDR_T_NONE) |
| 795 | return ERR_PTR(-EINVAL); |
| 796 | |
| 797 | return addr; |
| 798 | } |
| 799 | |
| 800 | static int rk3399_clk_probe(struct udevice *dev) |
| 801 | { |
| 802 | struct rk3399_clk_priv *priv = dev_get_priv(dev); |
| 803 | |
| 804 | rkclk_init(priv->cru); |
| 805 | |
| 806 | return 0; |
| 807 | } |
| 808 | |
| 809 | static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) |
| 810 | { |
| 811 | struct rk3399_clk_priv *priv = dev_get_priv(dev); |
| 812 | |
| 813 | priv->cru = (struct rk3399_cru *)dev_get_addr(dev); |
| 814 | |
| 815 | return 0; |
| 816 | } |
| 817 | |
| 818 | static int rk3399_clk_bind(struct udevice *dev) |
| 819 | { |
| 820 | int ret; |
| 821 | |
| 822 | /* The reset driver does not have a device node, so bind it here */ |
| 823 | ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev); |
| 824 | if (ret) |
| 825 | printf("Warning: No RK3399 reset driver: ret=%d\n", ret); |
| 826 | |
| 827 | return 0; |
| 828 | } |
| 829 | |
| 830 | static const struct udevice_id rk3399_clk_ids[] = { |
| 831 | { .compatible = "rockchip,rk3399-cru" }, |
| 832 | { } |
| 833 | }; |
| 834 | |
| 835 | U_BOOT_DRIVER(clk_rk3399) = { |
| 836 | .name = "clk_rk3399", |
| 837 | .id = UCLASS_CLK, |
| 838 | .of_match = rk3399_clk_ids, |
| 839 | .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), |
| 840 | .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, |
| 841 | .ops = &rk3399_clk_ops, |
| 842 | .bind = rk3399_clk_bind, |
| 843 | .probe = rk3399_clk_probe, |
| 844 | }; |
Kever Yang | e54d26a | 2016-08-12 17:47:15 +0800 | [diff] [blame] | 845 | |
| 846 | static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) |
| 847 | { |
| 848 | u32 div, con; |
| 849 | |
| 850 | switch (clk_id) { |
| 851 | case SCLK_I2C0_PMU: |
| 852 | con = readl(&pmucru->pmucru_clksel[2]); |
| 853 | div = I2C_CLK_DIV_VALUE(con, 0); |
| 854 | break; |
| 855 | case SCLK_I2C4_PMU: |
| 856 | con = readl(&pmucru->pmucru_clksel[3]); |
| 857 | div = I2C_CLK_DIV_VALUE(con, 4); |
| 858 | break; |
| 859 | case SCLK_I2C8_PMU: |
| 860 | con = readl(&pmucru->pmucru_clksel[2]); |
| 861 | div = I2C_CLK_DIV_VALUE(con, 8); |
| 862 | break; |
| 863 | default: |
| 864 | printf("do not support this i2c bus\n"); |
| 865 | return -EINVAL; |
| 866 | } |
| 867 | |
| 868 | return DIV_TO_RATE(PPLL_HZ, div); |
| 869 | } |
| 870 | |
| 871 | static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, |
| 872 | uint hz) |
| 873 | { |
| 874 | int src_clk_div; |
| 875 | |
| 876 | src_clk_div = PPLL_HZ / hz; |
| 877 | assert(src_clk_div - 1 < 127); |
| 878 | |
| 879 | switch (clk_id) { |
| 880 | case SCLK_I2C0_PMU: |
| 881 | rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), |
| 882 | I2C_PMUCLK_REG_VALUE(0, src_clk_div)); |
| 883 | break; |
| 884 | case SCLK_I2C4_PMU: |
| 885 | rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), |
| 886 | I2C_PMUCLK_REG_VALUE(4, src_clk_div)); |
| 887 | break; |
| 888 | case SCLK_I2C8_PMU: |
| 889 | rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), |
| 890 | I2C_PMUCLK_REG_VALUE(8, src_clk_div)); |
| 891 | break; |
| 892 | default: |
| 893 | printf("do not support this i2c bus\n"); |
| 894 | return -EINVAL; |
| 895 | } |
| 896 | |
| 897 | return DIV_TO_RATE(PPLL_HZ, src_clk_div); |
| 898 | } |
| 899 | |
| 900 | static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) |
| 901 | { |
| 902 | u32 div, con; |
| 903 | |
| 904 | /* PWM closk rate is same as pclk_pmu */ |
| 905 | con = readl(&pmucru->pmucru_clksel[0]); |
| 906 | div = con & PMU_PCLK_DIV_CON_MASK; |
| 907 | |
| 908 | return DIV_TO_RATE(PPLL_HZ, div); |
| 909 | } |
| 910 | |
| 911 | static ulong rk3399_pmuclk_get_rate(struct clk *clk) |
| 912 | { |
| 913 | struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); |
| 914 | ulong rate = 0; |
| 915 | |
| 916 | switch (clk->id) { |
| 917 | case PCLK_RKPWM_PMU: |
| 918 | rate = rk3399_pwm_get_clk(priv->pmucru); |
| 919 | break; |
| 920 | case SCLK_I2C0_PMU: |
| 921 | case SCLK_I2C4_PMU: |
| 922 | case SCLK_I2C8_PMU: |
| 923 | rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); |
| 924 | break; |
| 925 | default: |
| 926 | return -ENOENT; |
| 927 | } |
| 928 | |
| 929 | return rate; |
| 930 | } |
| 931 | |
| 932 | static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) |
| 933 | { |
| 934 | struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); |
| 935 | ulong ret = 0; |
| 936 | |
| 937 | switch (clk->id) { |
| 938 | case SCLK_I2C0_PMU: |
| 939 | case SCLK_I2C4_PMU: |
| 940 | case SCLK_I2C8_PMU: |
| 941 | ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); |
| 942 | break; |
| 943 | default: |
| 944 | return -ENOENT; |
| 945 | } |
| 946 | |
| 947 | return ret; |
| 948 | } |
| 949 | |
| 950 | static struct clk_ops rk3399_pmuclk_ops = { |
| 951 | .get_rate = rk3399_pmuclk_get_rate, |
| 952 | .set_rate = rk3399_pmuclk_set_rate, |
| 953 | }; |
| 954 | |
| 955 | static void pmuclk_init(struct rk3399_pmucru *pmucru) |
| 956 | { |
| 957 | u32 pclk_div; |
| 958 | |
| 959 | /* configure pmu pll(ppll) */ |
| 960 | rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); |
| 961 | |
| 962 | /* configure pmu pclk */ |
| 963 | pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; |
| 964 | assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); |
| 965 | rk_clrsetreg(&pmucru->pmucru_clksel[0], |
| 966 | PMU_PCLK_DIV_CON_MASK, |
| 967 | pclk_div << PMU_PCLK_DIV_CON_SHIFT); |
| 968 | } |
| 969 | |
| 970 | static int rk3399_pmuclk_probe(struct udevice *dev) |
| 971 | { |
| 972 | struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); |
| 973 | |
| 974 | pmuclk_init(priv->pmucru); |
| 975 | |
| 976 | return 0; |
| 977 | } |
| 978 | |
| 979 | static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) |
| 980 | { |
| 981 | struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); |
| 982 | |
| 983 | priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev); |
| 984 | |
| 985 | return 0; |
| 986 | } |
| 987 | |
| 988 | static const struct udevice_id rk3399_pmuclk_ids[] = { |
| 989 | { .compatible = "rockchip,rk3399-pmucru" }, |
| 990 | { } |
| 991 | }; |
| 992 | |
| 993 | U_BOOT_DRIVER(pmuclk_rk3399) = { |
| 994 | .name = "pmuclk_rk3399", |
| 995 | .id = UCLASS_CLK, |
| 996 | .of_match = rk3399_pmuclk_ids, |
| 997 | .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), |
| 998 | .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, |
| 999 | .ops = &rk3399_pmuclk_ops, |
| 1000 | .probe = rk3399_pmuclk_probe, |
| 1001 | }; |