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Masahiro Yamada3de725b2015-12-16 10:54:07 +09001/*
2 * Device Tree Source commonly used by UniPhier ARM SoCs
3 *
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+ X11
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
Masahiro Yamada224e2f72016-02-02 21:11:33 +090012 clocks {
13 refclk: ref {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 };
17 };
18
Masahiro Yamada3de725b2015-12-16 10:54:07 +090019 soc: soc {
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
24 interrupt-parent = <&intc>;
Masahiro Yamada1174603f2016-06-29 19:38:56 +090025 u-boot,dm-pre-reloc;
Masahiro Yamada3de725b2015-12-16 10:54:07 +090026
Masahiro Yamada3de725b2015-12-16 10:54:07 +090027 serial0: serial@54006800 {
28 compatible = "socionext,uniphier-uart";
29 status = "disabled";
30 reg = <0x54006800 0x40>;
31 interrupts = <0 33 4>;
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_uart0>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +090034 clocks = <&peri_clk 0>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +090035 };
36
37 serial1: serial@54006900 {
38 compatible = "socionext,uniphier-uart";
39 status = "disabled";
40 reg = <0x54006900 0x40>;
41 interrupts = <0 35 4>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_uart1>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +090044 clocks = <&peri_clk 1>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +090045 };
46
47 serial2: serial@54006a00 {
48 compatible = "socionext,uniphier-uart";
49 status = "disabled";
50 reg = <0x54006a00 0x40>;
51 interrupts = <0 37 4>;
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_uart2>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +090054 clocks = <&peri_clk 2>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +090055 };
56
57 serial3: serial@54006b00 {
58 compatible = "socionext,uniphier-uart";
59 status = "disabled";
60 reg = <0x54006b00 0x40>;
61 interrupts = <0 177 4>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_uart3>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +090064 clocks = <&peri_clk 3>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +090065 };
66
Masahiro Yamada94c12bf2016-02-16 17:00:22 +090067 system_bus: system-bus@58c00000 {
68 compatible = "socionext,uniphier-system-bus";
Masahiro Yamada1174603f2016-06-29 19:38:56 +090069 status = "disabled";
Masahiro Yamada94c12bf2016-02-16 17:00:22 +090070 reg = <0x58c00000 0x400>;
71 #address-cells = <2>;
72 #size-cells = <1>;
Masahiro Yamada1174603f2016-06-29 19:38:56 +090073 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_system_bus>;
Masahiro Yamada94c12bf2016-02-16 17:00:22 +090075 };
76
77 smpctrl@59800000 {
78 compatible = "socionext,uniphier-smpctrl";
79 reg = <0x59801000 0x400>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +090080 };
81
Masahiro Yamada02bf5b82016-09-22 07:42:23 +090082 mioctrl@59810000 {
83 compatible = "socionext,uniphier-mioctrl",
84 "simple-mfd", "syscon";
Masahiro Yamada1d5df7b2016-02-02 21:11:36 +090085 reg = <0x59810000 0x800>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +090086 u-boot,dm-pre-reloc;
87
88 mio_clk: clock {
89 #clock-cells = <1>;
90 };
91
92 mio_rst: reset {
93 #reset-cells = <1>;
94 };
Masahiro Yamada1d5df7b2016-02-02 21:11:36 +090095 };
96
Masahiro Yamada02bf5b82016-09-22 07:42:23 +090097 perictrl@59820000 {
98 compatible = "socionext,uniphier-perictrl",
99 "simple-mfd", "syscon";
Masahiro Yamada80951832016-02-02 21:11:35 +0900100 reg = <0x59820000 0x200>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +0900101
102 peri_clk: clock {
103 #clock-cells = <1>;
104 };
105
106 peri_rst: reset {
107 #reset-cells = <1>;
108 };
Masahiro Yamada80951832016-02-02 21:11:35 +0900109 };
110
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900111 timer@60000200 {
112 compatible = "arm,cortex-a9-global-timer";
113 reg = <0x60000200 0x20>;
114 interrupts = <1 11 0x104>;
115 clocks = <&arm_timer_clk>;
116 };
117
118 timer@60000600 {
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0x60000600 0x20>;
121 interrupts = <1 13 0x104>;
122 clocks = <&arm_timer_clk>;
123 };
124
125 intc: interrupt-controller@60001000 {
126 compatible = "arm,cortex-a9-gic";
127 reg = <0x60001000 0x1000>,
128 <0x60000100 0x100>;
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 };
132
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900133 soc-glue@5f800000 {
Masahiro Yamada02bf5b82016-09-22 07:42:23 +0900134 compatible = "socionext,uniphier-soc-glue",
135 "simple-mfd", "syscon";
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900136 reg = <0x5f800000 0x2000>;
137 u-boot,dm-pre-reloc;
138
139 pinctrl: pinctrl {
140 /* specify compatible in each SoC DTSI */
141 u-boot,dm-pre-reloc;
142 };
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900143 };
144
Masahiro Yamada02bf5b82016-09-22 07:42:23 +0900145 sysctrl@61840000 {
146 compatible = "socionext,uniphier-sysctrl",
147 "simple-mfd", "syscon";
Masahiro Yamadae84513b2016-02-02 21:11:34 +0900148 reg = <0x61840000 0x4000>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +0900149
150 sys_clk: clock {
151 #clock-cells = <1>;
152 };
153
154 sys_rst: reset {
155 #reset-cells = <1>;
156 };
Masahiro Yamadae84513b2016-02-02 21:11:34 +0900157 };
158
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900159 nand: nand@68000000 {
160 compatible = "denali,denali-nand-dt";
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900161 status = "disabled";
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900162 reg-names = "nand_data", "denali_reg";
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900163 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
164 interrupts = <0 65 4>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_nand>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900167 };
168 };
169};
170
171/include/ "uniphier-pinctrl.dtsi"