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git01.mediatek.com / filogic / uboot / f9db3b3b64f12d9f0c35f3f631f9284677157b77 / . / arch / arm / mach-socfpga / include / mach / sdram_gen5.h
blob: c41208591a1f03523afe8e9155bbafd3fde12c44 [file] [log] [blame]
Tom Rini4606fc72018-05-20 09:47:45 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tien Fong Chee38fad172017-12-05 15:58:00 +0800[diff] [blame]2/*
3 * Copyright Altera Corporation (C) 2014-2015
Tien Fong Chee38fad172017-12-05 15:58:00 +0800[diff] [blame]4 */
5#ifndef _SOCFPGA_SDRAM_GEN5_H_
6#define _SOCFPGA_SDRAM_GEN5_H_
7
8#ifndef __ASSEMBLY__
9
Tien Fong Chee38fad172017-12-05 15:58:00 +0800[diff] [blame]10const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
11
12void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
13void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
14const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
15const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
16const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
17
18#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
19
20struct socfpga_sdr_ctrl {
21 u32 ctrl_cfg;
22 u32 dram_timing1;
23 u32 dram_timing2;
24 u32 dram_timing3;
25 u32 dram_timing4; /* 0x10 */
26 u32 lowpwr_timing;
27 u32 dram_odt;
28 u32 extratime1;
29 u32 __padding0[3];
30 u32 dram_addrw; /* 0x2c */
31 u32 dram_if_width; /* 0x30 */
32 u32 dram_dev_width;
33 u32 dram_sts;
34 u32 dram_intr;
35 u32 sbe_count; /* 0x40 */
36 u32 dbe_count;
37 u32 err_addr;
38 u32 drop_count;
39 u32 drop_addr; /* 0x50 */
40 u32 lowpwr_eq;
41 u32 lowpwr_ack;
42 u32 static_cfg;
43 u32 ctrl_width; /* 0x60 */
44 u32 cport_width;
45 u32 cport_wmap;
46 u32 cport_rmap;
47 u32 rfifo_cmap; /* 0x70 */
48 u32 wfifo_cmap;
49 u32 cport_rdwr;
50 u32 port_cfg;
51 u32 fpgaport_rst; /* 0x80 */
52 u32 __padding1;
53 u32 fifo_cfg;
54 u32 protport_default;
55 u32 prot_rule_addr; /* 0x90 */
56 u32 prot_rule_id;
57 u32 prot_rule_data;
58 u32 prot_rule_rdwr;
59 u32 __padding2[3];
60 u32 mp_priority; /* 0xac */
61 u32 mp_weight0; /* 0xb0 */
62 u32 mp_weight1;
63 u32 mp_weight2;
64 u32 mp_weight3;
65 u32 mp_pacing0; /* 0xc0 */
66 u32 mp_pacing1;
67 u32 mp_pacing2;
68 u32 mp_pacing3;
69 u32 mp_threshold0; /* 0xd0 */
70 u32 mp_threshold1;
71 u32 mp_threshold2;
72 u32 __padding3[29];
73 u32 phy_ctrl0; /* 0x150 */
74 u32 phy_ctrl1;
75 u32 phy_ctrl2;
76};
77
78/* SDRAM configuration structure for the SPL. */
79struct socfpga_sdram_config {
80 u32 ctrl_cfg;
81 u32 dram_timing1;
82 u32 dram_timing2;
83 u32 dram_timing3;
84 u32 dram_timing4;
85 u32 lowpwr_timing;
86 u32 dram_odt;
87 u32 extratime1;
88 u32 dram_addrw;
89 u32 dram_if_width;
90 u32 dram_dev_width;
91 u32 dram_intr;
92 u32 lowpwr_eq;
93 u32 static_cfg;
94 u32 ctrl_width;
95 u32 cport_width;
96 u32 cport_wmap;
97 u32 cport_rmap;
98 u32 rfifo_cmap;
99 u32 wfifo_cmap;
100 u32 cport_rdwr;
101 u32 port_cfg;
102 u32 fpgaport_rst;
103 u32 fifo_cfg;
104 u32 mp_priority;
105 u32 mp_weight0;
106 u32 mp_weight1;
107 u32 mp_weight2;
108 u32 mp_weight3;
109 u32 mp_pacing0;
110 u32 mp_pacing1;
111 u32 mp_pacing2;
112 u32 mp_pacing3;
113 u32 mp_threshold0;
114 u32 mp_threshold1;
115 u32 mp_threshold2;
116 u32 phy_ctrl0;
117};
118
119struct socfpga_sdram_rw_mgr_config {
120 u8 activate_0_and_1;
121 u8 activate_0_and_1_wait1;
122 u8 activate_0_and_1_wait2;
123 u8 activate_1;
124 u8 clear_dqs_enable;
125 u8 guaranteed_read;
126 u8 guaranteed_read_cont;
127 u8 guaranteed_write;
128 u8 guaranteed_write_wait0;
129 u8 guaranteed_write_wait1;
130 u8 guaranteed_write_wait2;
131 u8 guaranteed_write_wait3;
132 u8 idle;
133 u8 idle_loop1;
134 u8 idle_loop2;
135 u8 init_reset_0_cke_0;
136 u8 init_reset_1_cke_0;
137 u8 lfsr_wr_rd_bank_0;
138 u8 lfsr_wr_rd_bank_0_data;
139 u8 lfsr_wr_rd_bank_0_dqs;
140 u8 lfsr_wr_rd_bank_0_nop;
141 u8 lfsr_wr_rd_bank_0_wait;
142 u8 lfsr_wr_rd_bank_0_wl_1;
143 u8 lfsr_wr_rd_dm_bank_0;
144 u8 lfsr_wr_rd_dm_bank_0_data;
145 u8 lfsr_wr_rd_dm_bank_0_dqs;
146 u8 lfsr_wr_rd_dm_bank_0_nop;
147 u8 lfsr_wr_rd_dm_bank_0_wait;
148 u8 lfsr_wr_rd_dm_bank_0_wl_1;
149 u8 mrs0_dll_reset;
150 u8 mrs0_dll_reset_mirr;
151 u8 mrs0_user;
152 u8 mrs0_user_mirr;
153 u8 mrs1;
154 u8 mrs1_mirr;
155 u8 mrs2;
156 u8 mrs2_mirr;
157 u8 mrs3;
158 u8 mrs3_mirr;
159 u8 precharge_all;
160 u8 read_b2b;
161 u8 read_b2b_wait1;
162 u8 read_b2b_wait2;
163 u8 refresh_all;
164 u8 rreturn;
165 u8 sgle_read;
166 u8 zqcl;
167
168 u8 true_mem_data_mask_width;
169 u8 mem_address_mirroring;
170 u8 mem_data_mask_width;
171 u8 mem_data_width;
172 u8 mem_dq_per_read_dqs;
173 u8 mem_dq_per_write_dqs;
174 u8 mem_if_read_dqs_width;
175 u8 mem_if_write_dqs_width;
176 u8 mem_number_of_cs_per_dimm;
177 u8 mem_number_of_ranks;
178 u8 mem_virtual_groups_per_read_dqs;
179 u8 mem_virtual_groups_per_write_dqs;
180};
181
182struct socfpga_sdram_io_config {
183 u16 delay_per_opa_tap;
184 u8 delay_per_dchain_tap;
185 u8 delay_per_dqs_en_dchain_tap;
186 u8 dll_chain_length;
187 u8 dqdqs_out_phase_max;
188 u8 dqs_en_delay_max;
189 u8 dqs_en_delay_offset;
190 u8 dqs_en_phase_max;
191 u8 dqs_in_delay_max;
192 u8 dqs_in_reserve;
193 u8 dqs_out_reserve;
194 u8 io_in_delay_max;
195 u8 io_out1_delay_max;
196 u8 io_out2_delay_max;
197 u8 shift_dqs_en_when_shift_dqs;
198};
199
200struct socfpga_sdram_misc_config {
201 u32 reg_file_init_seq_signature;
202 u8 afi_rate_ratio;
203 u8 calib_lfifo_offset;
204 u8 calib_vfifo_offset;
205 u8 enable_super_quick_calibration;
206 u8 max_latency_count_width;
207 u8 read_valid_fifo_size;
208 u8 tinit_cntr0_val;
209 u8 tinit_cntr1_val;
210 u8 tinit_cntr2_val;
211 u8 treset_cntr0_val;
212 u8 treset_cntr1_val;
213 u8 treset_cntr2_val;
214};
215
216#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
217#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
218#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
219#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
220#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
221#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
222#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
223#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
224#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
225#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
226#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
227#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
228#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
229#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
230#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
231#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
232#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
233#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
234/* Register template: sdr::ctrlgrp::dramtiming1 */
235#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
236#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
237#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
238#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
239#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
240#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
241#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
242#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
243#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
244#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
245#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
246#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
247/* Register template: sdr::ctrlgrp::dramtiming2 */
248#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
249#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
250#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
251#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
252#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
253#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
254#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
255#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
256#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
257#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
258/* Register template: sdr::ctrlgrp::dramtiming3 */
259#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
260#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
261#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
262#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
263#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
264#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
265#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
266#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
267#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
268#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
269/* Register template: sdr::ctrlgrp::dramtiming4 */
270#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
271#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
272#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
273#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
274#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
275#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
276/* Register template: sdr::ctrlgrp::lowpwrtiming */
277#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
278#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
279#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
280#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
281/* Register template: sdr::ctrlgrp::dramaddrw */
282#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
283#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
284#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
285#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
286#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
287#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
288#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
289#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
290/* Register template: sdr::ctrlgrp::dramifwidth */
291#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
292#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
293/* Register template: sdr::ctrlgrp::dramdevwidth */
294#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
295#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
296/* Register template: sdr::ctrlgrp::dramintr */
297#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
298#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
299#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
300#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
301/* Register template: sdr::ctrlgrp::staticcfg */
302#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
303#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
304#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
305#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
306#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
307#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
308/* Register template: sdr::ctrlgrp::ctrlwidth */
309#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
310#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
311/* Register template: sdr::ctrlgrp::cportwidth */
312#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
313#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
314/* Register template: sdr::ctrlgrp::cportwmap */
315#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
316#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
317/* Register template: sdr::ctrlgrp::cportrmap */
318#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
319#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
320/* Register template: sdr::ctrlgrp::rfifocmap */
321#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
322#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
323/* Register template: sdr::ctrlgrp::wfifocmap */
324#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
325#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
326/* Register template: sdr::ctrlgrp::cportrdwr */
327#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
328#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
329/* Register template: sdr::ctrlgrp::portcfg */
330#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
331#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
332#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
333#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
334/* Register template: sdr::ctrlgrp::fifocfg */
335#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
336#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
337#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
338#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
339/* Register template: sdr::ctrlgrp::mppriority */
340#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
341#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
342/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
343#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
344#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
345/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
346#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
347#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
348#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
349#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
350/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
351#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
352#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
353/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
354#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
355#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
356/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
357#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
358#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
359/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
360#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
361#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
362#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
363#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
364/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
365#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
366#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
367/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
368#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
369#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
370/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
371#define \
372SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
373#define \
374SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
3750xffffffff
376/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
377#define \
378SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
379#define \
380SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
3810xffffffff
382/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
383#define \
384SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
385#define \
386SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
3870x0000ffff
388/* Register template: sdr::ctrlgrp::remappriority */
389#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
390#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
391/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
392#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
393#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
394#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
395 (((x) << 12) & 0xfffff000)
396#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
397 (((x) << 10) & 0x00000c00)
398#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
399 (((x) << 6) & 0x000000c0)
400#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
401 (((x) << 8) & 0x00000100)
402#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
403 (((x) << 9) & 0x00000200)
404#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
405 (((x) << 4) & 0x00000030)
406#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
407 (((x) << 2) & 0x0000000c)
408#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
409 (((x) << 0) & 0x00000003)
410/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
411#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
412#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
413 (((x) << 12) & 0xfffff000)
414#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
415 (((x) << 0) & 0x00000fff)
416/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
417#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
418 (((x) << 0) & 0x00000fff)
419/* Register template: sdr::ctrlgrp::dramodt */
420#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
421#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
422#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
423#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
424/* Field instance: sdr::ctrlgrp::dramsts */
425#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
426#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
427/* Register template: sdr::ctrlgrp::extratime1 */
428#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
429#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
430#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
431
432/* SDRAM width macro for configuration with ECC */
433#define SDRAM_WIDTH_32BIT_WITH_ECC 40
434#define SDRAM_WIDTH_16BIT_WITH_ECC 24
435
436#endif
437#endif /* _SOCFPGA_SDRAM_GEN5_H_ */