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git01.mediatek.com / filogic / uboot / f9cd5b20073261ea90f8a14373254834005cce17 / . / arch / arm / include / asm / arch-rockchip / cru_rk3568.h
blob: 9c7ddd751f725b837d0660095bff7716f840bea6 [file] [log] [blame]
Elaine Zhang5be90bb2021-06-02 11:39:24 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6
7#ifndef _ASM_ARCH_CRU_RK3568_H
8#define _ASM_ARCH_CRU_RK3568_H
9
10#define MHz 1000000
11#define KHz 1000
12#define OSC_HZ (24 * MHz)
13
14#define APLL_HZ (816 * MHz)
15#define GPLL_HZ (1188 * MHz)
16#define CPLL_HZ (1000 * MHz)
Elaine Zhang7b9b9262021-10-12 16:43:00 +0800[diff] [blame]17#define PPLL_HZ (200 * MHz)
Elaine Zhang5be90bb2021-06-02 11:39:24 +0800[diff] [blame]18
19/* RK3568 pll id */
20enum rk3568_pll_id {
21 APLL,
22 DPLL,
23 CPLL,
24 GPLL,
25 NPLL,
26 VPLL,
27 PPLL,
28 HPLL,
29 PLL_COUNT,
30};
31
32struct rk3568_clk_info {
33 unsigned long id;
34 char *name;
35 bool is_cru;
36};
37
38/* Private data for the clock driver - used by rockchip_get_cru() */
39struct rk3568_pmuclk_priv {
40 struct rk3568_pmucru *pmucru;
41 ulong ppll_hz;
42 ulong hpll_hz;
43};
44
45struct rk3568_clk_priv {
46 struct rk3568_cru *cru;
47 struct rk3568_grf *grf;
48 ulong ppll_hz;
49 ulong hpll_hz;
50 ulong gpll_hz;
51 ulong cpll_hz;
52 ulong npll_hz;
53 ulong vpll_hz;
54 ulong armclk_hz;
55 ulong armclk_enter_hz;
56 ulong armclk_init_hz;
57 bool sync_kernel;
58 bool set_armclk_rate;
59};
60
61struct rk3568_pll {
62 unsigned int con0;
63 unsigned int con1;
64 unsigned int con2;
65 unsigned int con3;
66 unsigned int con4;
67 unsigned int reserved0[3];
68};
69
70struct rk3568_pmucru {
71 struct rk3568_pll pll[2];/* Address Offset: 0x0000 */
72 unsigned int reserved0[16];/* Address Offset: 0x0040 */
73 unsigned int mode_con00;/* Address Offset: 0x0080 */
74 unsigned int reserved1[31];/* Address Offset: 0x0084 */
75 unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
76 unsigned int reserved2[22];/* Address Offset: 0x0128 */
77 unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
78 unsigned int reserved3[29];/* Address Offset: 0x018C */
79 unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
80};
81
82check_member(rk3568_pmucru, mode_con00, 0x80);
83check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
84
85struct rk3568_cru {
86 struct rk3568_pll pll[6];
87 unsigned int mode_con00;/* Address Offset: 0x00C0 */
88 unsigned int misc_con[3];/* Address Offset: 0x00C4 */
89 unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
90 unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
91 unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
92 unsigned int glb_rst_con;/* Address Offset: 0x00DC */
93 unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
94 unsigned int reserved0[7];/* Address Offset: 0x00E4 */
95 unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
96 unsigned int reserved1[43];/* Address Offset: 0x0254 */
97 unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
98 unsigned int reserved2[28]; /* Address Offset: 0x0390 */
99 unsigned int softrst_con[30];/* Address Offset: 0x0400 */
100 unsigned int reserved3[2];/* Address Offset: 0x0478 */
101 unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
102 unsigned int reserved4[32];/* Address Offset: 0x0500 */
103 unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
104 unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
105 unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
106 unsigned int emmc_con[2];/* Address Offset: 0x0598 */
107};
108
Anton9a95efd2023-08-07 10:04:46 +0300[diff] [blame]109#define rockchip_cru rk3568_cru
110
Elaine Zhang5be90bb2021-06-02 11:39:24 +0800[diff] [blame]111check_member(rk3568_cru, mode_con00, 0xc0);
112check_member(rk3568_cru, softrst_con[0], 0x400);
113
114struct pll_rate_table {
115 unsigned long rate;
116 unsigned int fbdiv;
117 unsigned int postdiv1;
118 unsigned int refdiv;
119 unsigned int postdiv2;
120 unsigned int dsmpd;
121 unsigned int frac;
122};
123
124#define RK3568_PMU_MODE 0x80
125#define RK3568_PMU_PLL_CON(x) ((x) * 0x4)
126#define RK3568_PLL_CON(x) ((x) * 0x4)
127#define RK3568_MODE_CON 0xc0
128
129enum {
130 /* CRU_PMU_CLK_SEL0_CON */
131 RTC32K_SEL_SHIFT = 6,
132 RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT,
133 RTC32K_SEL_PMUPVTM = 0,
134 RTC32K_SEL_OSC1_32K,
135 RTC32K_SEL_OSC0_DIV32K,
136
137 /* CRU_PMU_CLK_SEL1_CON */
138 RTC32K_FRAC_NUMERATOR_SHIFT = 16,
139 RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16,
140 RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
141 RTC32K_FRAC_DENOMINATOR_MASK = 0xffff,
142
143 /* CRU_PMU_CLK_SEL2_CON */
144 PCLK_PDPMU_SEL_SHIFT = 15,
145 PCLK_PDPMU_SEL_MASK = 1 << PCLK_PDPMU_SEL_SHIFT,
146 PCLK_PDPMU_SEL_PPLL = 0,
147 PCLK_PDPMU_SEL_GPLL,
148 PCLK_PDPMU_DIV_SHIFT = 0,
149 PCLK_PDPMU_DIV_MASK = 0x1f,
150
151 /* CRU_PMU_CLK_SEL3_CON */
152 CLK_I2C0_DIV_SHIFT = 0,
153 CLK_I2C0_DIV_MASK = 0x7f,
154
155 /* CRU_PMU_CLK_SEL6_CON */
156 CLK_PWM0_SEL_SHIFT = 7,
157 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
158 CLK_PWM0_SEL_XIN24M = 0,
159 CLK_PWM0_SEL_PPLL,
160 CLK_PWM0_DIV_SHIFT = 0,
161 CLK_PWM0_DIV_MASK = 0x7f,
162
163 /* CRU_CLK_SEL0_CON */
164 CLK_CORE_PRE_SEL_SHIFT = 7,
165 CLK_CORE_PRE_SEL_MASK = 1 << CLK_CORE_PRE_SEL_SHIFT,
166 CLK_CORE_PRE_SEL_SRC = 0,
167 CLK_CORE_PRE_SEL_APLL,
168
169 /* CRU_CLK_SEL2_CON */
170 SCLK_CORE_PRE_SEL_SHIFT = 15,
171 SCLK_CORE_PRE_SEL_MASK = 1 << SCLK_CORE_PRE_SEL_SHIFT,
172 SCLK_CORE_PRE_SEL_SRC = 0,
173 SCLK_CORE_PRE_SEL_NPLL,
174 SCLK_CORE_SRC_SEL_SHIFT = 8,
175 SCLK_CORE_SRC_SEL_MASK = 3 << SCLK_CORE_SRC_SEL_SHIFT,
176 SCLK_CORE_SRC_SEL_APLL = 0,
177 SCLK_CORE_SRC_SEL_GPLL,
178 SCLK_CORE_SRC_SEL_NPLL,
179 SCLK_CORE_SRC_DIV_SHIFT = 0,
180 SCLK_CORE_SRC_DIV_MASK = 0x1f << SCLK_CORE_SRC_DIV_SHIFT,
181
182 /* CRU_CLK_SEL3_CON */
183 GICCLK_CORE_DIV_SHIFT = 8,
184 GICCLK_CORE_DIV_MASK = 0x1f << GICCLK_CORE_DIV_SHIFT,
185 ATCLK_CORE_DIV_SHIFT = 0,
186 ATCLK_CORE_DIV_MASK = 0x1f << ATCLK_CORE_DIV_SHIFT,
187
188 /* CRU_CLK_SEL4_CON */
189 PERIPHCLK_CORE_PRE_DIV_SHIFT = 8,
190 PERIPHCLK_CORE_PRE_DIV_MASK = 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT,
191 PCLK_CORE_PRE_DIV_SHIFT = 0,
192 PCLK_CORE_PRE_DIV_MASK = 0x1f << PCLK_CORE_PRE_DIV_SHIFT,
193
194 /* CRU_CLK_SEL5_CON */
195 ACLK_CORE_NIU2BUS_SEL_SHIFT = 14,
196 ACLK_CORE_NIU2BUS_SEL_MASK = 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT,
197 ACLK_CORE_NDFT_DIV_SHIFT = 8,
198 ACLK_CORE_NDFT_DIV_MASK = 0x1f << ACLK_CORE_NDFT_DIV_SHIFT,
199
200 /* CRU_CLK_SEL10_CON */
201 HCLK_PERIMID_SEL_SHIFT = 6,
202 HCLK_PERIMID_SEL_MASK = 3 << HCLK_PERIMID_SEL_SHIFT,
203 HCLK_PERIMID_SEL_150M = 0,
204 HCLK_PERIMID_SEL_100M,
205 HCLK_PERIMID_SEL_75M,
206 HCLK_PERIMID_SEL_24M,
207 ACLK_PERIMID_SEL_SHIFT = 4,
208 ACLK_PERIMID_SEL_MASK = 3 << ACLK_PERIMID_SEL_SHIFT,
209 ACLK_PERIMID_SEL_300M = 0,
210 ACLK_PERIMID_SEL_200M,
211 ACLK_PERIMID_SEL_100M,
212 ACLK_PERIMID_SEL_24M,
213
214 /* CRU_CLK_SEL27_CON */
215 CLK_CRYPTO_PKA_SEL_SHIFT = 6,
216 CLK_CRYPTO_PKA_SEL_MASK = 3 << CLK_CRYPTO_PKA_SEL_SHIFT,
217 CLK_CRYPTO_PKA_SEL_300M = 0,
218 CLK_CRYPTO_PKA_SEL_200M,
219 CLK_CRYPTO_PKA_SEL_100M,
220 CLK_CRYPTO_CORE_SEL_SHIFT = 4,
221 CLK_CRYPTO_CORE_SEL_MASK = 3 << CLK_CRYPTO_CORE_SEL_SHIFT,
222 CLK_CRYPTO_CORE_SEL_200M = 0,
223 CLK_CRYPTO_CORE_SEL_150M,
224 CLK_CRYPTO_CORE_SEL_100M,
225 HCLK_SECURE_FLASH_SEL_SHIFT = 2,
226 HCLK_SECURE_FLASH_SEL_MASK = 3 << HCLK_SECURE_FLASH_SEL_SHIFT,
227 HCLK_SECURE_FLASH_SEL_150M = 0,
228 HCLK_SECURE_FLASH_SEL_100M,
229 HCLK_SECURE_FLASH_SEL_75M,
230 HCLK_SECURE_FLASH_SEL_24M,
231 ACLK_SECURE_FLASH_SEL_SHIFT = 0,
232 ACLK_SECURE_FLASH_SEL_MASK = 3 << ACLK_SECURE_FLASH_SEL_SHIFT,
233 ACLK_SECURE_FLASH_SEL_200M = 0,
234 ACLK_SECURE_FLASH_SEL_150M,
235 ACLK_SECURE_FLASH_SEL_100M,
236 ACLK_SECURE_FLASH_SEL_24M,
237
238 /* CRU_CLK_SEL28_CON */
239 CCLK_EMMC_SEL_SHIFT = 12,
240 CCLK_EMMC_SEL_MASK = 7 << CCLK_EMMC_SEL_SHIFT,
241 CCLK_EMMC_SEL_24M = 0,
242 CCLK_EMMC_SEL_200M,
243 CCLK_EMMC_SEL_150M,
244 CCLK_EMMC_SEL_100M,
245 CCLK_EMMC_SEL_50M,
246 CCLK_EMMC_SEL_375K,
247 BCLK_EMMC_SEL_SHIFT = 8,
248 BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT,
249 BCLK_EMMC_SEL_200M = 0,
250 BCLK_EMMC_SEL_150M,
251 BCLK_EMMC_SEL_125M,
252 SCLK_SFC_SEL_SHIFT = 4,
253 SCLK_SFC_SEL_MASK = 7 << SCLK_SFC_SEL_SHIFT,
254 SCLK_SFC_SEL_24M = 0,
255 SCLK_SFC_SEL_50M,
256 SCLK_SFC_SEL_75M,
257 SCLK_SFC_SEL_100M,
258 SCLK_SFC_SEL_125M,
259 SCLK_SFC_SEL_150M,
260 NCLK_NANDC_SEL_SHIFT = 0,
261 NCLK_NANDC_SEL_MASK = 3 << NCLK_NANDC_SEL_SHIFT,
262 NCLK_NANDC_SEL_200M = 0,
263 NCLK_NANDC_SEL_150M,
264 NCLK_NANDC_SEL_100M,
265 NCLK_NANDC_SEL_24M,
266
267 /* CRU_CLK_SEL30_CON */
268 CLK_SDMMC1_SEL_SHIFT = 12,
269 CLK_SDMMC1_SEL_MASK = 7 << CLK_SDMMC1_SEL_SHIFT,
270 CLK_SDMMC0_SEL_SHIFT = 8,
271 CLK_SDMMC0_SEL_MASK = 7 << CLK_SDMMC0_SEL_SHIFT,
272 CLK_SDMMC_SEL_24M = 0,
273 CLK_SDMMC_SEL_400M,
274 CLK_SDMMC_SEL_300M,
275 CLK_SDMMC_SEL_100M,
276 CLK_SDMMC_SEL_50M,
277 CLK_SDMMC_SEL_750K,
278
279 /* CRU_CLK_SEL31_CON */
280 CLK_MAC0_OUT_SEL_SHIFT = 14,
281 CLK_MAC0_OUT_SEL_MASK = 3 << CLK_MAC0_OUT_SEL_SHIFT,
282 CLK_MAC0_OUT_SEL_125M = 0,
283 CLK_MAC0_OUT_SEL_50M,
284 CLK_MAC0_OUT_SEL_25M,
285 CLK_MAC0_OUT_SEL_24M,
286 CLK_GMAC0_PTP_REF_SEL_SHIFT = 12,
287 CLK_GMAC0_PTP_REF_SEL_MASK = 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT,
288 CLK_GMAC0_PTP_REF_SEL_62_5M = 0,
289 CLK_GMAC0_PTP_REF_SEL_100M,
290 CLK_GMAC0_PTP_REF_SEL_50M,
291 CLK_GMAC0_PTP_REF_SEL_24M,
292 CLK_MAC0_2TOP_SEL_SHIFT = 8,
293 CLK_MAC0_2TOP_SEL_MASK = 3 << CLK_MAC0_2TOP_SEL_SHIFT,
294 CLK_MAC0_2TOP_SEL_125M = 0,
295 CLK_MAC0_2TOP_SEL_50M,
296 CLK_MAC0_2TOP_SEL_25M,
297 CLK_MAC0_2TOP_SEL_PPLL,
298 RGMII0_CLK_SEL_SHIFT = 4,
299 RGMII0_CLK_SEL_MASK = 3 << RGMII0_CLK_SEL_SHIFT,
300 RGMII0_CLK_SEL_125M = 0,
301 RGMII0_CLK_SEL_125M_1,
302 RGMII0_CLK_SEL_2_5M,
303 RGMII0_CLK_SEL_25M,
304 RMII0_CLK_SEL_SHIFT = 3,
305 RMII0_CLK_SEL_MASK = 1 << RMII0_CLK_SEL_SHIFT,
306 RMII0_CLK_SEL_2_5M = 0,
307 RMII0_CLK_SEL_25M,
308 RMII0_EXTCLK_SEL_SHIFT = 2,
309 RMII0_EXTCLK_SEL_MASK = 1 << RMII0_EXTCLK_SEL_SHIFT,
310 RMII0_EXTCLK_SEL_MAC0_TOP = 0,
311 RMII0_EXTCLK_SEL_IO,
312 RMII0_MODE_SHIFT = 0,
313 RMII0_MODE_MASK = 3 << RMII0_MODE_SHIFT,
314 RMII0_MODE_SEL_RGMII = 0,
315 RMII0_MODE_SEL_RMII,
316 RMII0_MODE_SEL_GMII,
317
318 /* CRU_CLK_SEL32_CON */
319 CLK_SDMMC2_SEL_SHIFT = 8,
320 CLK_SDMMC2_SEL_MASK = 7 << CLK_SDMMC2_SEL_SHIFT,
321
322 /* CRU_CLK_SEL38_CON */
323 ACLK_VOP_PRE_SEL_SHIFT = 6,
324 ACLK_VOP_PRE_SEL_MASK = 3 << ACLK_VOP_PRE_SEL_SHIFT,
325 ACLK_VOP_PRE_SEL_CPLL = 0,
326 ACLK_VOP_PRE_SEL_GPLL,
327 ACLK_VOP_PRE_SEL_HPLL,
328 ACLK_VOP_PRE_SEL_VPLL,
329 ACLK_VOP_PRE_DIV_SHIFT = 0,
330 ACLK_VOP_PRE_DIV_MASK = 0x1f << ACLK_VOP_PRE_DIV_SHIFT,
331
332 /* CRU_CLK_SEL39_CON */
333 DCLK0_VOP_SEL_SHIFT = 10,
334 DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT,
335 DCLK_VOP_SEL_HPLL = 0,
336 DCLK_VOP_SEL_VPLL,
337 DCLK_VOP_SEL_GPLL,
338 DCLK_VOP_SEL_CPLL,
339 DCLK0_VOP_DIV_SHIFT = 0,
340 DCLK0_VOP_DIV_MASK = 0xff << DCLK0_VOP_DIV_SHIFT,
341
342 /* CRU_CLK_SEL40_CON */
343 DCLK1_VOP_SEL_SHIFT = 10,
344 DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT,
345 DCLK1_VOP_DIV_SHIFT = 0,
346 DCLK1_VOP_DIV_MASK = 0xff << DCLK1_VOP_DIV_SHIFT,
347
348 /* CRU_CLK_SEL41_CON */
349 DCLK2_VOP_SEL_SHIFT = 10,
350 DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT,
351 DCLK2_VOP_DIV_SHIFT = 0,
352 DCLK2_VOP_DIV_MASK = 0xff << DCLK2_VOP_DIV_SHIFT,
353
354 /* CRU_CLK_SEL43_CON */
355 DCLK_EBC_SEL_SHIFT = 6,
356 DCLK_EBC_SEL_MASK = 3 << DCLK_EBC_SEL_SHIFT,
357 DCLK_EBC_SEL_GPLL_400M = 0,
358 DCLK_EBC_SEL_CPLL_333M,
359 DCLK_EBC_SEL_GPLL_200M,
360
361 /* CRU_CLK_SEL47_CON */
362 ACLK_RKVDEC_SEL_SHIFT = 7,
363 ACLK_RKVDEC_SEL_MASK = 1 << ACLK_RKVDEC_SEL_SHIFT,
364 ACLK_RKVDEC_SEL_GPLL = 0,
365 ACLK_RKVDEC_SEL_CPLL,
366 ACLK_RKVDEC_DIV_SHIFT = 0,
367 ACLK_RKVDEC_DIV_MASK = 0x1f << ACLK_RKVDEC_DIV_SHIFT,
368
369 /* CRU_CLK_SEL49_CON */
370 CLK_RKVDEC_CORE_SEL_SHIFT = 14,
371 CLK_RKVDEC_CORE_SEL_MASK = 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT,
372 CLK_RKVDEC_CORE_SEL_GPLL = 0,
373 CLK_RKVDEC_CORE_SEL_CPLL,
374 CLK_RKVDEC_CORE_SEL_NPLL,
375 CLK_RKVDEC_CORE_SEL_VPLL,
376 CLK_RKVDEC_CORE_DIV_SHIFT = 8,
377 CLK_RKVDEC_CORE_DIV_MASK = 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT,
378
379 /* CRU_CLK_SEL50_CON */
380 PCLK_BUS_SEL_SHIFT = 4,
381 PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT,
382 PCLK_BUS_SEL_100M = 0,
383 PCLK_BUS_SEL_75M,
384 PCLK_BUS_SEL_50M,
385 PCLK_BUS_SEL_24M,
386 ACLK_BUS_SEL_SHIFT = 0,
387 ACLK_BUS_SEL_MASK = 3 << ACLK_BUS_SEL_SHIFT,
388 ACLK_BUS_SEL_200M = 0,
389 ACLK_BUS_SEL_150M,
390 ACLK_BUS_SEL_100M,
391 ACLK_BUS_SEL_24M,
392
393 /* CRU_CLK_SEL51_CON */
394 CLK_TSADC_DIV_SHIFT = 8,
395 CLK_TSADC_DIV_MASK = 0x7f << CLK_TSADC_DIV_SHIFT,
396 CLK_TSADC_TSEN_SEL_SHIFT = 4,
397 CLK_TSADC_TSEN_SEL_MASK = 0x3 << CLK_TSADC_TSEN_SEL_SHIFT,
398 CLK_TSADC_TSEN_SEL_24M = 0,
399 CLK_TSADC_TSEN_SEL_100M,
400 CLK_TSADC_TSEN_SEL_CPLL_100M,
401 CLK_TSADC_TSEN_DIV_SHIFT = 0,
402 CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT,
403
404 /* CRU_CLK_SEL52_CON */
405 CLK_UART_SEL_SHIFT = 12,
406 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
407 CLK_UART_SEL_SRC = 0,
408 CLK_UART_SEL_FRAC,
409 CLK_UART_SEL_XIN24M,
410 CLK_UART_SRC_SEL_SHIFT = 8,
411 CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT,
412 CLK_UART_SRC_SEL_GPLL = 0,
413 CLK_UART_SRC_SEL_CPLL,
414 CLK_UART_SRC_SEL_480M,
415 CLK_UART_SRC_DIV_SHIFT = 0,
416 CLK_UART_SRC_DIV_MASK = 0x3f << CLK_UART_SRC_DIV_SHIFT,
417
418 /* CRU_CLK_SEL53_CON */
419 CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
420 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
421 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
422 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
423
424 /* CRU_CLK_SEL71_CON */
425 CLK_I2C_SEL_SHIFT = 8,
426 CLK_I2C_SEL_MASK = 3 << CLK_I2C_SEL_SHIFT,
427 CLK_I2C_SEL_200M = 0,
428 CLK_I2C_SEL_100M,
429 CLK_I2C_SEL_24M,
430 CLK_I2C_SEL_CPLL_100M,
431
432 /* CRU_CLK_SEL72_CON */
433 CLK_PWM3_SEL_SHIFT = 12,
434 CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT,
435 CLK_PWM2_SEL_SHIFT = 10,
436 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
437 CLK_PWM1_SEL_SHIFT = 8,
438 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
439 CLK_PWM_SEL_100M = 0,
440 CLK_PWM_SEL_24M,
441 CLK_PWM_SEL_CPLL_100M,
442 CLK_SPI3_SEL_SHIFT = 6,
443 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
444 CLK_SPI2_SEL_SHIFT = 4,
445 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
446 CLK_SPI1_SEL_SHIFT = 2,
447 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
448 CLK_SPI0_SEL_SHIFT = 0,
449 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
450 CLK_SPI_SEL_200M = 0,
451 CLK_SPI_SEL_24M,
452 CLK_SPI_SEL_CPLL_100M,
453
454 /* CRU_CLK_SEL73_CON */
455 PCLK_TOP_SEL_SHIFT = 12,
456 PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT,
457 PCLK_TOP_SEL_100M = 0,
458 PCLK_TOP_SEL_75M,
459 PCLK_TOP_SEL_50M,
460 PCLK_TOP_SEL_24M,
461 HCLK_TOP_SEL_SHIFT = 8,
462 HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT,
463 HCLK_TOP_SEL_150M = 0,
464 HCLK_TOP_SEL_100M,
465 HCLK_TOP_SEL_75M,
466 HCLK_TOP_SEL_24M,
467 ACLK_TOP_LOW_SEL_SHIFT = 4,
468 ACLK_TOP_LOW_SEL_MASK = 3 << ACLK_TOP_LOW_SEL_SHIFT,
469 ACLK_TOP_LOW_SEL_400M = 0,
470 ACLK_TOP_LOW_SEL_300M,
471 ACLK_TOP_LOW_SEL_200M,
472 ACLK_TOP_LOW_SEL_24M,
473 ACLK_TOP_HIGH_SEL_SHIFT = 0,
474 ACLK_TOP_HIGH_SEL_MASK = 3 << ACLK_TOP_HIGH_SEL_SHIFT,
475 ACLK_TOP_HIGH_SEL_500M = 0,
476 ACLK_TOP_HIGH_SEL_400M,
477 ACLK_TOP_HIGH_SEL_300M,
478 ACLK_TOP_HIGH_SEL_24M,
479
480 /* CRU_CLK_SEL78_CON */
481 CPLL_500M_DIV_SHIFT = 8,
482 CPLL_500M_DIV_MASK = 0x1f << CPLL_500M_DIV_SHIFT,
483
484 /* CRU_CLK_SEL79_CON */
485 CPLL_250M_DIV_SHIFT = 8,
486 CPLL_250M_DIV_MASK = 0x1f << CPLL_250M_DIV_SHIFT,
487 CPLL_333M_DIV_SHIFT = 0,
488 CPLL_333M_DIV_MASK = 0x1f << CPLL_333M_DIV_SHIFT,
489
490 /* CRU_CLK_SEL80_CON */
491 CPLL_62P5M_DIV_SHIFT = 8,
492 CPLL_62P5M_DIV_MASK = 0x1f << CPLL_62P5M_DIV_SHIFT,
493 CPLL_125M_DIV_SHIFT = 0,
494 CPLL_125M_DIV_MASK = 0x1f << CPLL_125M_DIV_SHIFT,
495
496 /* CRU_CLK_SEL81_CON */
497 CPLL_25M_DIV_SHIFT = 8,
Jonas Karlmanf51ca5c2023-08-04 09:33:59 +0000[diff] [blame]498 CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT,
Elaine Zhang5be90bb2021-06-02 11:39:24 +0800[diff] [blame]499 CPLL_50M_DIV_SHIFT = 0,
500 CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT,
501
502 /* CRU_CLK_SEL82_CON */
503 CPLL_100M_DIV_SHIFT = 0,
504 CPLL_100M_DIV_MASK = 0x1f << CPLL_100M_DIV_SHIFT,
505};
506#endif