| Jim Liu | ca0be9e | 2023-01-17 16:59:23 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | |
| 3 | #ifndef _NPCM_RNG_H_ |
| 4 | #define _NPCM_RNG_H_ |
| 5 | |
| 6 | struct npcm_rng_regs { |
| 7 | unsigned int rngcs; |
| 8 | unsigned int rngd; |
| 9 | unsigned int rngmode; |
| 10 | }; |
| 11 | |
| 12 | #define RNGCS_RNGE (1 << 0) |
| 13 | #define RNGCS_DVALID (1 << 1) |
| 14 | #define RNGCS_CLKP(range) ((0x0f & (range)) << 2) |
| 15 | #define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I */ |
| 16 | |
| 17 | /*----------------------------------------------------------------------------*/ |
| 18 | /* Core Domain Clock Frequency Range for the selected value is higher */ |
| 19 | /* than or equal to the actual Core domain clock frequency */ |
| 20 | /*----------------------------------------------------------------------------*/ |
| 21 | enum { |
| 22 | RNG_CLKP_80_100_MHZ = 0x00, /*default */ |
| 23 | RNG_CLKP_60_80_MHZ = 0x01, |
| 24 | RNG_CLKP_50_60_MHZ = 0x02, |
| 25 | RNG_CLKP_40_50_MHZ = 0x03, |
| 26 | RNG_CLKP_30_40_MHZ = 0x04, |
| 27 | RNG_CLKP_25_30_MHZ = 0x05, |
| 28 | RNG_CLKP_20_25_MHZ = 0x06, |
| 29 | RNG_CLKP_5_20_MHZ = 0x07, |
| 30 | RNG_CLKP_2_15_MHZ = 0x08, |
| 31 | RNG_CLKP_9_12_MHZ = 0x09, |
| 32 | RNG_CLKP_7_9_MHZ = 0x0A, |
| 33 | RNG_CLKP_6_7_MHZ = 0x0B, |
| 34 | RNG_CLKP_5_6_MHZ = 0x0C, |
| 35 | RNG_CLKP_4_5_MHZ = 0x0D, |
| 36 | RNG_CLKP_3_4_MHZ = 0x0E, |
| 37 | RNG_NUM_OF_CLKP |
| 38 | }; |
| 39 | |
| 40 | void npcm_rng_init(void); |
| 41 | void npcm_rng_disable(void); |
| 42 | |
| 43 | #endif |