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Wolfgang Denk994ad962006-10-24 14:42:37 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk994ad962006-10-24 14:42:37 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann94156fa2010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoen23f62f12008-05-19 11:36:28 +020012
Andreas Bießmannf40a5b72011-04-18 04:12:36 +000013#define CONFIG_AT32AP
14#define CONFIG_AT32AP7000
15#define CONFIG_ATSTK1002
16#define CONFIG_ATSTK1000
Wolfgang Denk994ad962006-10-24 14:42:37 +020017
Wolfgang Denk994ad962006-10-24 14:42:37 +020018/*
Eirik Aanonsen96775342007-09-12 13:32:37 +020019 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
20 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
21 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020022 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Wolfgang Denk994ad962006-10-24 14:42:37 +020023 */
Andreas Bießmannf40a5b72011-04-18 04:12:36 +000024#define CONFIG_PLL
25#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020026#define CONFIG_SYS_OSC0_HZ 20000000
27#define CONFIG_SYS_PLL0_DIV 1
28#define CONFIG_SYS_PLL0_MUL 7
29#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Eirik Aanonsen96775342007-09-12 13:32:37 +020030/*
31 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Eirik Aanonsen96775342007-09-12 13:32:37 +020033 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034#define CONFIG_SYS_CLKDIV_CPU 0
Eirik Aanonsen96775342007-09-12 13:32:37 +020035/*
36 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Eirik Aanonsen96775342007-09-12 13:32:37 +020038 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039#define CONFIG_SYS_CLKDIV_HSB 1
Eirik Aanonsen96775342007-09-12 13:32:37 +020040/*
41 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Eirik Aanonsen96775342007-09-12 13:32:37 +020043 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_CLKDIV_PBA 2
Eirik Aanonsen96775342007-09-12 13:32:37 +020045/*
46 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Eirik Aanonsen96775342007-09-12 13:32:37 +020048 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_CLKDIV_PBB 1
Wolfgang Denk994ad962006-10-24 14:42:37 +020050
Haavard Skinnemoenc6f292f2010-08-12 13:52:54 +070051/* Reserve VM regions for SDRAM and NOR flash */
52#define CONFIG_SYS_NR_VM_REGIONS 2
53
Wolfgang Denk994ad962006-10-24 14:42:37 +020054/*
55 * The PLLOPT register controls the PLL like this:
56 * icp = PLLOPT<2>
57 * ivco = PLLOPT<1:0>
58 *
59 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
60 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_PLL0_OPT 0x04
Wolfgang Denk994ad962006-10-24 14:42:37 +020062
Andreas Bießmann5807e792010-11-04 23:15:31 +000063#define CONFIG_USART_BASE ATMEL_BASE_USART1
64#define CONFIG_USART_ID 1
Wolfgang Denk994ad962006-10-24 14:42:37 +020065
66/* User serviceable stuff */
Andreas Bießmannf40a5b72011-04-18 04:12:36 +000067#define CONFIG_DOS_PARTITION
Haavard Skinnemoene034f522006-12-17 18:56:46 +010068
Andreas Bießmannf40a5b72011-04-18 04:12:36 +000069#define CONFIG_CMDLINE_TAG
70#define CONFIG_SETUP_MEMORY_TAGS
71#define CONFIG_INITRD_TAG
Wolfgang Denk994ad962006-10-24 14:42:37 +020072
73#define CONFIG_STACKSIZE (2048)
74
75#define CONFIG_BAUDRATE 115200
76#define CONFIG_BOOTARGS \
Eirik Aanonsenb4ba6c62007-09-18 08:47:20 +020077 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
Haavard Skinnemoen1ec84272007-03-21 19:47:36 +010078
79#define CONFIG_BOOTCOMMAND \
80 "fsload; bootm $(fileaddr)"
81
Wolfgang Denk994ad962006-10-24 14:42:37 +020082
Haavard Skinnemoen58f4c262006-12-17 17:14:30 +010083/*
Haavard Skinnemoenb4d85022007-10-24 15:48:37 +020084 * After booting the board for the first time, new ethernet addresses
85 * should be generated and assigned to the environment variables
86 * "ethaddr" and "eth1addr". This is normally done during production.
Haavard Skinnemoen58f4c262006-12-17 17:14:30 +010087 */
Andreas Bießmannf40a5b72011-04-18 04:12:36 +000088#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoen58f4c262006-12-17 17:14:30 +010089
Jon Loeligerdcf14512007-07-09 21:48:26 -050090/*
91 * BOOTP options
92 */
93#define CONFIG_BOOTP_SUBNETMASK
94#define CONFIG_BOOTP_GATEWAY
95
Andreas Bießmann66392342015-02-06 23:06:50 +010096/* generic board */
Andreas Bießmann66392342015-02-06 23:06:50 +010097#define CONFIG_BOARD_EARLY_INIT_F
98#define CONFIG_BOARD_EARLY_INIT_R
Wolfgang Denk994ad962006-10-24 14:42:37 +020099
Jon Loeligerc5707f52007-07-04 22:31:42 -0500100/*
101 * Command line configuration.
102 */
Jon Loeligerc5707f52007-07-04 22:31:42 -0500103#define CONFIG_CMD_JFFS2
Jon Loeligerc5707f52007-07-04 22:31:42 -0500104
Andreas Bießmannf40a5b72011-04-18 04:12:36 +0000105#define CONFIG_ATMEL_USART
106#define CONFIG_MACB
107#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmannf40a5b72011-04-18 04:12:36 +0000109#define CONFIG_SYS_HSDRAMC
110#define CONFIG_MMC
Sven Schnelle8aa96822011-10-21 14:49:25 +0200111#define CONFIG_GENERIC_ATMEL_MCI
112#define CONFIG_GENERIC_MMC
Wolfgang Denk994ad962006-10-24 14:42:37 +0200113
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_DCACHE_LINESZ 32
115#define CONFIG_SYS_ICACHE_LINESZ 32
Wolfgang Denk994ad962006-10-24 14:42:37 +0200116
117#define CONFIG_NR_DRAM_BANKS 1
118
Andreas Bießmannab7344a2011-06-28 04:15:58 +0000119#define CONFIG_SYS_FLASH_CFI
120#define CONFIG_FLASH_CFI_DRIVER
Wolfgang Denk994ad962006-10-24 14:42:37 +0200121
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BASE 0x00000000
123#define CONFIG_SYS_FLASH_SIZE 0x800000
124#define CONFIG_SYS_MAX_FLASH_BANKS 1
125#define CONFIG_SYS_MAX_FLASH_SECT 135
Wolfgang Denk994ad962006-10-24 14:42:37 +0200126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann71c2bf52011-04-18 04:12:44 +0000128#define CONFIG_SYS_TEXT_BASE 0x00000000
Wolfgang Denk994ad962006-10-24 14:42:37 +0200129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
131#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
132#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Wolfgang Denk994ad962006-10-24 14:42:37 +0200133
Andreas Bießmannf40a5b72011-04-18 04:12:36 +0000134#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200135#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Wolfgang Denk994ad962006-10-24 14:42:37 +0200137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Wolfgang Denk994ad962006-10-24 14:42:37 +0200139
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_MALLOC_LEN (256*1024)
Haavard Skinnemoenabf19bf2006-11-20 15:53:10 +0100141
Haavard Skinnemoen141cf5e2007-11-22 17:01:24 +0100142/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
144#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Wolfgang Denk994ad962006-10-24 14:42:37 +0200145
146/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_CBSIZE 256
148#define CONFIG_SYS_MAXARGS 16
149#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmannf40a5b72011-04-18 04:12:36 +0000150#define CONFIG_SYS_LONGHELP
Wolfgang Denk994ad962006-10-24 14:42:37 +0200151
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
153#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
154#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Wolfgang Denk994ad962006-10-24 14:42:37 +0200155
156#endif /* __CONFIG_H */