blob: f9cda5eec7d2e23c5149cc9a0435358723ff7041 [file] [log] [blame]
Oliver Grauteabf0e7b2023-04-21 12:11:50 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2017-2019 NXP
4 * Copyright 2019-2023 Kococonnector GmbH
5 */
6
7#ifndef __IMX8QM_DMSSE20_H
8#define __IMX8QM_DMSSE20_H
9
10#include <linux/sizes.h>
11#include <asm/arch/imx-regs.h>
12
13/* Flat Device Tree Definitions */
14
15#define CFG_SYS_FSL_ESDHC_ADDR 0
16#define USDHC1_BASE_ADDR 0x5B010000
17#define USDHC2_BASE_ADDR 0x5B020000
18#define USDHC3_BASE_ADDR 0x5B030000
19
20#define FEC_QUIRK_ENET_MAC
21
22#define IMX_FEC_BASE 0x5B040000
23/* FEC1 */
24#define IMX_FEC1_BASE 0x5B040000
25/* FEC2 */
26#define IMX_FEC2_BASE 0x5B050000
27
28#ifdef CONFIG_NAND_BOOT
29#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
30#else
31#define MFG_NAND_PARTITION ""
32#endif
33
34/* Incorporate settings into the U-Boot environment */
35#define CFG_EXTRA_ENV_SETTINGS
36
37#define CFG_SYS_FSL_USDHC_NUM 2
38
39#define CFG_SYS_SDRAM_BASE 0x080000000
40#define PHYS_SDRAM_1 0x080000000
41#define PHYS_SDRAM_2 0x880000000
42#define PHYS_SDRAM_1_SIZE 0x080000000 /* 2 GB */
43#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */
44
45/* Generic Timer Definitions */
46#define COUNTER_FREQUENCY 8000000 /* 8MHz */
47
48#endif /* __IMX8QM_DMSSE20_H */