| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/spi/arm,pl022-peripheral-props.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Peripheral-specific properties for Arm PL022 SPI controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Linus Walleij <linus.walleij@linaro.org> |
| 11 | |
| 12 | select: false |
| 13 | |
| 14 | properties: |
| 15 | pl022,interface: |
| 16 | description: SPI interface type |
| 17 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 18 | enum: |
| 19 | - 0 # SPI |
| 20 | - 1 # Texas Instruments Synchronous Serial Frame Format |
| 21 | - 2 # Microwire (Half Duplex) |
| 22 | |
| 23 | pl022,com-mode: |
| 24 | description: Specifies the transfer mode |
| 25 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 26 | enum: |
| 27 | - 0 # interrupt mode |
| 28 | - 1 # polling mode |
| 29 | - 2 # DMA mode |
| 30 | default: 1 |
| 31 | |
| 32 | pl022,rx-level-trig: |
| 33 | description: Rx FIFO watermark level |
| 34 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 35 | minimum: 0 |
| 36 | maximum: 4 |
| 37 | |
| 38 | pl022,tx-level-trig: |
| 39 | description: Tx FIFO watermark level |
| 40 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 41 | minimum: 0 |
| 42 | maximum: 4 |
| 43 | |
| 44 | pl022,ctrl-len: |
| 45 | description: Microwire interface - Control length |
| 46 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 47 | minimum: 0x03 |
| 48 | maximum: 0x1f |
| 49 | |
| 50 | pl022,wait-state: |
| 51 | description: Microwire interface - Wait state |
| 52 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 53 | enum: [0, 1] |
| 54 | |
| 55 | pl022,duplex: |
| 56 | description: Microwire interface - Full/Half duplex |
| 57 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 58 | enum: [0, 1] |
| 59 | |
| 60 | additionalProperties: true |
| 61 | ... |