| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Socionext UniPhier USB3 Super-Speed (SS) PHY |
| 8 | |
| 9 | description: | |
| 10 | This describes the devicetree bindings for PHY interfaces built into |
| 11 | USB3 controller implemented on Socionext UniPhier SoCs. |
| 12 | Although the controller includes High-Speed PHY and Super-Speed PHY, |
| 13 | this describes about Super-Speed PHY. |
| 14 | |
| 15 | maintainers: |
| 16 | - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | enum: |
| 21 | - socionext,uniphier-pro4-usb3-ssphy |
| 22 | - socionext,uniphier-pro5-usb3-ssphy |
| 23 | - socionext,uniphier-pxs2-usb3-ssphy |
| 24 | - socionext,uniphier-ld20-usb3-ssphy |
| 25 | - socionext,uniphier-pxs3-usb3-ssphy |
| 26 | - socionext,uniphier-nx1-usb3-ssphy |
| 27 | |
| 28 | reg: |
| 29 | maxItems: 1 |
| 30 | |
| 31 | "#phy-cells": |
| 32 | const: 0 |
| 33 | |
| 34 | clocks: |
| 35 | minItems: 2 |
| 36 | maxItems: 3 |
| 37 | |
| 38 | clock-names: true |
| 39 | |
| 40 | resets: |
| 41 | maxItems: 2 |
| 42 | |
| 43 | reset-names: true |
| 44 | |
| 45 | vbus-supply: |
| 46 | description: A phandle to the regulator for USB VBUS, only for USB host |
| 47 | |
| 48 | allOf: |
| 49 | - if: |
| 50 | properties: |
| 51 | compatible: |
| 52 | contains: |
| 53 | enum: |
| 54 | - socionext,uniphier-pro4-usb3-ssphy |
| 55 | - socionext,uniphier-pro5-usb3-ssphy |
| 56 | then: |
| 57 | properties: |
| 58 | clocks: |
| 59 | minItems: 2 |
| 60 | maxItems: 2 |
| 61 | clock-names: |
| 62 | items: |
| 63 | - const: gio |
| 64 | - const: link |
| 65 | resets: |
| 66 | minItems: 2 |
| 67 | maxItems: 2 |
| 68 | reset-names: |
| 69 | items: |
| 70 | - const: gio |
| 71 | - const: link |
| 72 | - if: |
| 73 | properties: |
| 74 | compatible: |
| 75 | contains: |
| 76 | enum: |
| 77 | - socionext,uniphier-pxs2-usb3-ssphy |
| 78 | - socionext,uniphier-ld20-usb3-ssphy |
| 79 | then: |
| 80 | properties: |
| 81 | clocks: |
| 82 | minItems: 2 |
| 83 | maxItems: 2 |
| 84 | clock-names: |
| 85 | items: |
| 86 | - const: link |
| 87 | - const: phy |
| 88 | resets: |
| 89 | minItems: 2 |
| 90 | maxItems: 2 |
| 91 | reset-names: |
| 92 | items: |
| 93 | - const: link |
| 94 | - const: phy |
| 95 | - if: |
| 96 | properties: |
| 97 | compatible: |
| 98 | contains: |
| 99 | enum: |
| 100 | - socionext,uniphier-pxs3-usb3-ssphy |
| 101 | - socionext,uniphier-nx1-usb3-ssphy |
| 102 | then: |
| 103 | properties: |
| 104 | clocks: |
| 105 | minItems: 2 |
| 106 | maxItems: 3 |
| 107 | clock-names: |
| 108 | minItems: 2 |
| 109 | items: |
| 110 | - const: link |
| 111 | - const: phy |
| 112 | - const: phy-ext |
| 113 | resets: |
| 114 | minItems: 2 |
| 115 | maxItems: 2 |
| 116 | reset-names: |
| 117 | items: |
| 118 | - const: link |
| 119 | - const: phy |
| 120 | |
| 121 | required: |
| 122 | - compatible |
| 123 | - reg |
| 124 | - "#phy-cells" |
| 125 | - clocks |
| 126 | - clock-names |
| 127 | - resets |
| 128 | - reset-names |
| 129 | |
| 130 | additionalProperties: false |
| 131 | |
| 132 | examples: |
| 133 | - | |
| 134 | usb_ssphy0: phy@300 { |
| 135 | compatible = "socionext,uniphier-ld20-usb3-ssphy"; |
| 136 | reg = <0x300 0x10>; |
| 137 | #phy-cells = <0>; |
| 138 | clock-names = "link", "phy"; |
| 139 | clocks = <&sys_clk 14>, <&sys_clk 16>; |
| 140 | reset-names = "link", "phy"; |
| 141 | resets = <&sys_rst 14>, <&sys_rst 16>; |
| 142 | vbus-supply = <&usb_vbus0>; |
| 143 | }; |