| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Socionext UniPhier PCIe PHY |
| 8 | |
| 9 | description: | |
| 10 | This describes the devicetree bindings for PHY interface built into |
| 11 | PCIe controller implemented on Socionext UniPhier SoCs. |
| 12 | |
| 13 | maintainers: |
| 14 | - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
| 15 | |
| 16 | properties: |
| 17 | compatible: |
| 18 | enum: |
| 19 | - socionext,uniphier-pro5-pcie-phy |
| 20 | - socionext,uniphier-ld20-pcie-phy |
| 21 | - socionext,uniphier-pxs3-pcie-phy |
| 22 | - socionext,uniphier-nx1-pcie-phy |
| 23 | |
| 24 | reg: |
| 25 | maxItems: 1 |
| 26 | |
| 27 | "#phy-cells": |
| 28 | const: 0 |
| 29 | |
| 30 | clocks: |
| 31 | minItems: 1 |
| 32 | maxItems: 2 |
| 33 | |
| 34 | clock-names: true |
| 35 | |
| 36 | resets: |
| 37 | minItems: 1 |
| 38 | maxItems: 2 |
| 39 | |
| 40 | reset-names: true |
| 41 | |
| 42 | socionext,syscon: |
| 43 | $ref: /schemas/types.yaml#/definitions/phandle |
| 44 | description: A phandle to system control to set configurations for phy |
| 45 | |
| 46 | allOf: |
| 47 | - if: |
| 48 | properties: |
| 49 | compatible: |
| 50 | contains: |
| 51 | const: socionext,uniphier-pro5-pcie-phy |
| 52 | then: |
| 53 | properties: |
| 54 | clocks: |
| 55 | minItems: 2 |
| 56 | maxItems: 2 |
| 57 | clock-names: |
| 58 | items: |
| 59 | - const: gio |
| 60 | - const: link |
| 61 | resets: |
| 62 | minItems: 2 |
| 63 | maxItems: 2 |
| 64 | reset-names: |
| 65 | items: |
| 66 | - const: gio |
| 67 | - const: link |
| 68 | else: |
| 69 | properties: |
| 70 | clocks: |
| 71 | maxItems: 1 |
| 72 | clock-names: |
| 73 | const: link |
| 74 | resets: |
| 75 | maxItems: 1 |
| 76 | reset-names: |
| 77 | const: link |
| 78 | |
| 79 | required: |
| 80 | - compatible |
| 81 | - reg |
| 82 | - "#phy-cells" |
| 83 | - clocks |
| 84 | - clock-names |
| 85 | - resets |
| 86 | - reset-names |
| 87 | |
| 88 | additionalProperties: false |
| 89 | |
| 90 | examples: |
| 91 | - | |
| 92 | pcie_phy: phy@66038000 { |
| 93 | compatible = "socionext,uniphier-ld20-pcie-phy"; |
| 94 | reg = <0x66038000 0x4000>; |
| 95 | #phy-cells = <0>; |
| 96 | clock-names = "link"; |
| 97 | clocks = <&sys_clk 24>; |
| 98 | reset-names = "link"; |
| 99 | resets = <&sys_rst 24>; |
| 100 | socionext,syscon = <&soc_glue>; |
| 101 | }; |