dts/upstream/Bindings/phy/phy-hisi-inno-usb2.txt

Device tree bindings for HiSilicon INNO USB2 PHY

Required properties:
- compatible: Should be one of the following strings:
	"hisilicon,inno-usb2-phy",
	"hisilicon,hi3798cv200-usb2-phy".
- reg: Should be the address space for PHY configuration register in peripheral
  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
  reference clock.
- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
  signal.
- #address-cells: Must be 1.
- #size-cells: Must be 0.

The INNO USB2 PHY device should be a child node of peripheral controller that
contains the PHY configuration register, and each device supports up to 2 PHY
ports which are represented as child nodes of INNO USB2 PHY device.

Required properties for PHY port node:
- reg: The PHY port instance number.
- #phy-cells: Defined by generic PHY bindings.  Must be 0.
- resets: The phandle and reset specifier pair for PHY port reset signal.

Refer to phy/phy-bindings.txt for the generic PHY binding properties

Example:

perictrl: peripheral-controller@8a20000 {
	compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
	reg = <0x8a20000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8a20000 0x1000>;

	usb2_phy1: usb2-phy@120 {
		compatible = "hisilicon,hi3798cv200-usb2-phy";
		reg = <0x120 0x4>;
		clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
		resets = <&crg 0xbc 4>;
		#address-cells = <1>;
		#size-cells = <0>;

		usb2_phy1_port0: phy@0 {
			reg = <0>;
			#phy-cells = <0>;
			resets = <&crg 0xbc 8>;
		};

		usb2_phy1_port1: phy@1 {
			reg = <1>;
			#phy-cells = <0>;
			resets = <&crg 0xbc 9>;
		};
	};

	usb2_phy2: usb2-phy@124 {
		compatible = "hisilicon,hi3798cv200-usb2-phy";
		reg = <0x124 0x4>;
		clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
		resets = <&crg 0xbc 6>;
		#address-cells = <1>;
		#size-cells = <0>;

		usb2_phy2_port0: phy@0 {
			reg = <0>;
			#phy-cells = <0>;
			resets = <&crg 0xbc 10>;
		};
	};
};