blob: f557feca97630ccc5cd0cc4cbdf47190296fb7e5 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A64 USB PHY
8
9maintainers:
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
12
13properties:
14 "#phy-cells":
15 const: 1
16
17 compatible:
18 enum:
19 - allwinner,sun20i-d1-usb-phy
20 - allwinner,sun50i-a64-usb-phy
21
22 reg:
23 items:
24 - description: PHY Control registers
25 - description: PHY PMU0 registers
26 - description: PHY PMU1 registers
27
28 reg-names:
29 items:
30 - const: phy_ctrl
31 - const: pmu0
32 - const: pmu1
33
34 clocks:
35 items:
36 - description: USB OTG PHY bus clock
37 - description: USB Host 0 PHY bus clock
38
39 clock-names:
40 items:
41 - const: usb0_phy
42 - const: usb1_phy
43
44 resets:
45 items:
46 - description: USB OTG reset
47 - description: USB Host 1 Controller reset
48
49 reset-names:
50 items:
51 - const: usb0_reset
52 - const: usb1_reset
53
54 usb0_id_det-gpios:
55 maxItems: 1
56 description: GPIO to the USB OTG ID pin
57
58 usb0_vbus_det-gpios:
59 maxItems: 1
60 description: GPIO to the USB OTG VBUS detect pin
61
62 usb0_vbus_power-supply:
63 description: Power supply to detect the USB OTG VBUS
64
65 usb0_vbus-supply:
66 description: Regulator controlling USB OTG VBUS
67
68 usb1_vbus-supply:
69 description: Regulator controlling USB1 Host controller
70
71required:
72 - "#phy-cells"
73 - compatible
74 - clocks
75 - clock-names
76 - reg
77 - reg-names
78 - resets
79 - reset-names
80
81additionalProperties: false
82
83examples:
84 - |
85 #include <dt-bindings/gpio/gpio.h>
86 #include <dt-bindings/clock/sun50i-a64-ccu.h>
87 #include <dt-bindings/reset/sun50i-a64-ccu.h>
88
89 phy@1c19400 {
90 #phy-cells = <1>;
91 compatible = "allwinner,sun50i-a64-usb-phy";
92 reg = <0x01c19400 0x14>,
93 <0x01c1a800 0x4>,
94 <0x01c1b800 0x4>;
95 reg-names = "phy_ctrl",
96 "pmu0",
97 "pmu1";
98 clocks = <&ccu CLK_USB_PHY0>,
99 <&ccu CLK_USB_PHY1>;
100 clock-names = "usb0_phy",
101 "usb1_phy";
102 resets = <&ccu RST_USB_PHY0>,
103 <&ccu RST_USB_PHY1>;
104 reset-names = "usb0_reset",
105 "usb1_reset";
106 usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
107 usb0_vbus_power-supply = <&usb_power_supply>;
108 usb0_vbus-supply = <&reg_drivevbus>;
109 usb1_vbus-supply = <&reg_usb1_vbus>;
110 };