| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/mux/reg-mux.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Generic register bitfield-based multiplexer controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Peter Rosin <peda@axentia.se> |
| 11 | |
| 12 | description: |+ |
| 13 | Define register bitfields to be used to control multiplexers. The parent |
| 14 | device tree node must be a device node to provide register r/w access. |
| 15 | |
| 16 | properties: |
| 17 | compatible: |
| 18 | enum: |
| 19 | - reg-mux # parent device of mux controller is not syscon device |
| 20 | - mmio-mux # parent device of mux controller is syscon device |
| 21 | |
| 22 | reg: true |
| 23 | |
| 24 | '#mux-control-cells': |
| 25 | const: 1 |
| 26 | |
| 27 | mux-reg-masks: |
| 28 | $ref: /schemas/types.yaml#/definitions/uint32-matrix |
| 29 | items: |
| 30 | items: |
| 31 | - description: register offset |
| 32 | - description: pre-shifted bitfield mask |
| 33 | description: Each entry pair describes a single mux control. |
| 34 | |
| 35 | idle-states: true |
| 36 | |
| 37 | required: |
| 38 | - compatible |
| 39 | - mux-reg-masks |
| 40 | - '#mux-control-cells' |
| 41 | |
| 42 | additionalProperties: false |
| 43 | |
| 44 | examples: |
| 45 | - | |
| 46 | /* The parent device of mux controller is not a syscon device. */ |
| 47 | |
| 48 | #include <dt-bindings/mux/mux.h> |
| 49 | |
| 50 | mux-controller { |
| 51 | compatible = "reg-mux"; |
| 52 | #mux-control-cells = <1>; |
| 53 | mux-reg-masks = |
| 54 | <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ |
| 55 | <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ |
| 56 | }; |
| 57 | |
| 58 | mdio-mux-1 { |
| 59 | compatible = "mdio-mux-multiplexer"; |
| 60 | mux-controls = <&mux1 0>; |
| 61 | mdio-parent-bus = <&emdio1>; |
| 62 | #address-cells = <1>; |
| 63 | #size-cells = <0>; |
| 64 | |
| 65 | mdio@0 { |
| 66 | reg = <0x0>; |
| 67 | #address-cells = <1>; |
| 68 | #size-cells = <0>; |
| 69 | }; |
| 70 | |
| 71 | mdio@8 { |
| 72 | reg = <0x8>; |
| 73 | #address-cells = <1>; |
| 74 | #size-cells = <0>; |
| 75 | }; |
| 76 | }; |
| 77 | |
| 78 | mdio-mux-2 { |
| 79 | compatible = "mdio-mux-multiplexer"; |
| 80 | mux-controls = <&mux1 1>; |
| 81 | mdio-parent-bus = <&emdio2>; |
| 82 | #address-cells = <1>; |
| 83 | #size-cells = <0>; |
| 84 | |
| 85 | mdio@0 { |
| 86 | reg = <0x0>; |
| 87 | #address-cells = <1>; |
| 88 | #size-cells = <0>; |
| 89 | }; |
| 90 | |
| 91 | mdio@1 { |
| 92 | reg = <0x1>; |
| 93 | #address-cells = <1>; |
| 94 | #size-cells = <0>; |
| 95 | }; |
| 96 | }; |
| 97 | |
| 98 | - | |
| 99 | /* The parent device of mux controller is syscon device. */ |
| 100 | |
| 101 | #include <dt-bindings/mux/mux.h> |
| 102 | syscon@1000 { |
| 103 | reg = <0x1000 0x100>; |
| 104 | |
| 105 | mux2: mux-controller { |
| 106 | compatible = "mmio-mux"; |
| 107 | #mux-control-cells = <1>; |
| 108 | |
| 109 | mux-reg-masks = |
| 110 | <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */ |
| 111 | <0x3 0x40>; /* 1: reg 0x3, bit 6 */ |
| 112 | idle-states = <MUX_IDLE_AS_IS>, <0>; |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | video-mux { |
| 117 | compatible = "video-mux"; |
| 118 | mux-controls = <&mux2 0>; |
| 119 | #address-cells = <1>; |
| 120 | #size-cells = <0>; |
| 121 | |
| 122 | ports { |
| 123 | #address-cells = <1>; |
| 124 | #size-cells = <0>; |
| 125 | |
| 126 | /* inputs 0..3 */ |
| 127 | port@0 { |
| 128 | reg = <0>; |
| 129 | }; |
| 130 | port@1 { |
| 131 | reg = <1>; |
| 132 | }; |
| 133 | port@2 { |
| 134 | reg = <2>; |
| 135 | }; |
| 136 | port@3 { |
| 137 | reg = <3>; |
| 138 | }; |
| 139 | |
| 140 | /* output */ |
| 141 | port@4 { |
| 142 | reg = <4>; |
| 143 | }; |
| 144 | }; |
| 145 | }; |
| 146 | ... |