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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hao Zhang82be0132014-07-16 00:59:27 +03002/*
3 * K2E EVM : Board initialization
4 *
5 * (C) Copyright 2014
6 * Texas Instruments Incorporated, <www.ti.com>
Hao Zhang82be0132014-07-16 00:59:27 +03007 */
8
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Hao Zhang82be0132014-07-16 00:59:27 +030011#include <asm/arch/ddr3.h>
12#include <asm/arch/hardware.h>
Hao Zhang6d4ec892014-10-17 21:01:17 +030013#include <asm/ti-common/keystone_net.h>
Hao Zhang82be0132014-07-16 00:59:27 +030014
Lokesh Vutlaa9a0e122017-05-03 16:58:26 +053015unsigned int get_external_clk(u32 clk)
16{
17 unsigned int clk_freq;
18
19 switch (clk) {
20 case sys_clk:
21 clk_freq = 100000000;
22 break;
23 case alt_core_clk:
24 clk_freq = 100000000;
25 break;
26 case pa_clk:
27 clk_freq = 100000000;
28 break;
29 case ddr3a_clk:
30 clk_freq = 100000000;
31 break;
32 default:
33 clk_freq = 0;
34 break;
35 }
36
37 return clk_freq;
38}
Hao Zhang82be0132014-07-16 00:59:27 +030039
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053040static struct pll_init_data core_pll_config[NUM_SPDS] = {
41 [SPD800] = CORE_PLL_800,
42 [SPD850] = CORE_PLL_850,
43 [SPD1000] = CORE_PLL_1000,
44 [SPD1250] = CORE_PLL_1250,
45 [SPD1350] = CORE_PLL_1350,
46 [SPD1400] = CORE_PLL_1400,
47 [SPD1500] = CORE_PLL_1500,
48};
49
50/* DEV and ARM speed definitions as specified in DEVSPEED register */
51int speeds[DEVSPEED_NUMSPDS] = {
52 SPD850,
53 SPD1000,
54 SPD1250,
55 SPD1350,
56 SPD1400,
57 SPD1500,
58 SPD1400,
59 SPD1350,
60 SPD1250,
61 SPD1000,
62 SPD850,
63 SPD800,
Hao Zhang82be0132014-07-16 00:59:27 +030064};
65
Lokesh Vutla70438fc2015-07-28 14:16:43 +053066s16 divn_val[16] = {
67 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
68};
69
Vitaly Andrianov047e7802014-07-25 22:23:19 +030070static struct pll_init_data pa_pll_config =
71 PASS_PLL_1000;
72
Lokesh Vutla79a94a22015-07-28 14:16:46 +053073struct pll_init_data *get_pll_init_data(int pll)
74{
75 int speed;
76 struct pll_init_data *data;
77
78 switch (pll) {
79 case MAIN_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060080 speed = get_max_dev_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053081 data = &core_pll_config[speed];
82 break;
83 case PASS_PLL:
84 data = &pa_pll_config;
85 break;
86 default:
87 data = NULL;
88 }
89
90 return data;
91}
92
Jean-Jacques Hiblot2037fa42017-09-15 12:57:24 +020093#if defined(CONFIG_MULTI_DTB_FIT)
Cooper Jr., Franklin43ff2242017-06-16 17:25:16 -050094int board_fit_config_name_match(const char *name)
95{
96 if (!strcmp(name, "keystone-k2e-evm"))
97 return 0;
98
99 return -1;
100}
101#endif
102
Hao Zhang82be0132014-07-16 00:59:27 +0300103#if defined(CONFIG_BOARD_EARLY_INIT_F)
104int board_early_init_f(void)
105{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530106 init_plls();
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300107
Hao Zhang82be0132014-07-16 00:59:27 +0300108 return 0;
109}
110#endif
Hao Zhang95948202014-10-22 16:32:31 +0300111
112#ifdef CONFIG_SPL_BUILD
Hao Zhang95948202014-10-22 16:32:31 +0300113void spl_init_keystone_plls(void)
114{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530115 init_plls();
Hao Zhang95948202014-10-22 16:32:31 +0300116}
117#endif