| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 Siemens Schweiz AG |
| 4 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 5 | * |
| 6 | * Based on: |
| Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 7 | * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ |
| Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 8 | */ |
| 9 | #ifndef PMIC_H |
| 10 | #define PMIC_H |
| 11 | |
| 12 | /* |
| 13 | * The PMIC on this board is a TPS65910. |
| 14 | */ |
| 15 | |
| 16 | #define PMIC_SR_I2C_ADDR 0x12 |
| 17 | #define PMIC_CTRL_I2C_ADDR 0x2D |
| 18 | /* PMIC Register offsets */ |
| 19 | #define PMIC_VDD1_REG 0x21 |
| 20 | #define PMIC_VDD1_OP_REG 0x22 |
| 21 | #define PMIC_VDD2_REG 0x24 |
| 22 | #define PMIC_VDD2_OP_REG 0x25 |
| 23 | #define PMIC_DEVCTRL_REG 0x3f |
| 24 | |
| 25 | /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ |
| 26 | #define PMIC_VGAIN_SEL_MASK (0x3 << 6) |
| 27 | #define PMIC_ILMAX_MASK (0x1 << 5) |
| 28 | #define PMIC_TSTEP_MASK (0x7 << 2) |
| 29 | #define PMIC_ST_MASK (0x3) |
| 30 | |
| 31 | #define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) |
| 32 | #define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) |
| 33 | #define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) |
| 34 | #define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) |
| 35 | |
| 36 | #define PMIC_REG_ILMAX_1_0_A (0x0 << 5) |
| 37 | #define PMIC_REG_ILMAX_1_5_A (0x1 << 5) |
| 38 | |
| 39 | #define PMIC_REG_TSTEP_ (0x0 << 2) |
| 40 | #define PMIC_REG_TSTEP_12_5 (0x1 << 2) |
| 41 | #define PMIC_REG_TSTEP_9_4 (0x2 << 2) |
| 42 | #define PMIC_REG_TSTEP_7_5 (0x3 << 2) |
| 43 | #define PMIC_REG_TSTEP_6_25 (0x4 << 2) |
| 44 | #define PMIC_REG_TSTEP_4_7 (0x5 << 2) |
| 45 | #define PMIC_REG_TSTEP_3_12 (0x6 << 2) |
| 46 | #define PMIC_REG_TSTEP_2_5 (0x7 << 2) |
| 47 | |
| 48 | #define PMIC_REG_ST_OFF (0x0) |
| 49 | #define PMIC_REG_ST_ON_HI_POW (0x1) |
| 50 | #define PMIC_REG_ST_OFF_1 (0x2) |
| 51 | #define PMIC_REG_ST_ON_LOW_POW (0x3) |
| 52 | |
| 53 | |
| 54 | /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ |
| 55 | #define PMIC_OP_REG_SEL (0x7F) |
| 56 | |
| 57 | #define PMIC_OP_REG_CMD_MASK (0x1 << 7) |
| 58 | #define PMIC_OP_REG_CMD_OP (0x0 << 7) |
| 59 | #define PMIC_OP_REG_CMD_SR (0x1 << 7) |
| 60 | |
| 61 | #define PMIC_OP_REG_SEL_MASK (0x7F) |
| 62 | #define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ |
| 63 | #define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ |
| 64 | |
| 65 | /* Device control register . (DEVCTRL_REG) */ |
| 66 | #define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) |
| 67 | #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) |
| 68 | #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) |
| 69 | |
| 70 | #endif |