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git01.mediatek.com / filogic / uboot / f94b26109b51f02fcd5930cfbbc24a865e6e4e81 / . / board / renesas / blanche / qos.c
blob: f0bc7f7698bcec8d6c1a795ac6cef953597f78c2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]2/*
3 * board/renesas/blanche/qos.c
4 *
5 * Copyright (C) 2016 Renesas Electronics Corporation
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]6 */
7
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]8#include <asm/processor.h>
9#include <asm/mach-types.h>
10#include <asm/io.h>
Marek Vasut97a070b2024-02-27 17:05:54 +0100[diff] [blame]11#include <asm/arch/renesas.h>
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]12
Marek Vasutd26aa8c2024-02-27 17:05:53 +0100[diff] [blame]13#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]14enum {
15 DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
16 DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
17 DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
18 DBSC3_15,
19 DBSC3_NR,
20};
21
22static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
23 [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
24 [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
25 [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
26 [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
27 [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
28 [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
29 [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
30 [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
31 [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
32 [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
33 [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
34 [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
35 [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
36 [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
37 [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
38 [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
39};
40
41static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
42 [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
43 [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
44 [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
45 [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
46 [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
47 [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
48 [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
49 [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
50 [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
51 [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
52 [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
53 [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
54 [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
55 [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
56 [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
57 [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
58};
59
60void qos_init(void)
61{
62 int i;
63 struct rcar_s3c *s3c;
64 struct rcar_s3c_qos *s3c_qos;
65 struct rcar_dbsc3_qos *qos_addr;
66 struct rcar_mxi *mxi;
67 struct rcar_mxi_qos *mxi_qos;
68 struct rcar_axi_qos *axi_qos;
69
70 /* DBSC DBADJ2 */
71 writel(0x20082004, DBSC3_0_DBADJ2);
72
73 /* S3C -QoS */
74 s3c = (struct rcar_s3c *)S3C_BASE;
75 // writel(0x00000000, &s3c->s3cadsplcr);
76 writel(0x1F0D0C0C, &s3c->s3crorr);
77 writel(0x1F1F0C0C, &s3c->s3cworr);
78
79 /* QoS Control Registers */
80 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
81 writel(0x00890089, &s3c_qos->s3cqos0);
82 writel(0x20960010, &s3c_qos->s3cqos1);
83 writel(0x20302030, &s3c_qos->s3cqos2);
84 writel(0x20AA2200, &s3c_qos->s3cqos3);
85 writel(0x00002032, &s3c_qos->s3cqos4);
86 writel(0x20960010, &s3c_qos->s3cqos5);
87 writel(0x20302030, &s3c_qos->s3cqos6);
88 writel(0x20AA2200, &s3c_qos->s3cqos7);
89 writel(0x00002032, &s3c_qos->s3cqos8);
90
91 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
92 writel(0x00890089, &s3c_qos->s3cqos0);
93 writel(0x20960010, &s3c_qos->s3cqos1);
94 writel(0x20302030, &s3c_qos->s3cqos2);
95 writel(0x20AA2200, &s3c_qos->s3cqos3);
96 writel(0x00002032, &s3c_qos->s3cqos4);
97 writel(0x20960010, &s3c_qos->s3cqos5);
98 writel(0x20302030, &s3c_qos->s3cqos6);
99 writel(0x20AA2200, &s3c_qos->s3cqos7);
100 writel(0x00002032, &s3c_qos->s3cqos8);
101
102 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
103 writel(0x00820082, &s3c_qos->s3cqos0);
104 writel(0x20960020, &s3c_qos->s3cqos1);
105 writel(0x20302030, &s3c_qos->s3cqos2);
106 writel(0x20AA20DC, &s3c_qos->s3cqos3);
107 writel(0x00002032, &s3c_qos->s3cqos4);
108 writel(0x20960020, &s3c_qos->s3cqos5);
109 writel(0x20302030, &s3c_qos->s3cqos6);
110 writel(0x20AA20DC, &s3c_qos->s3cqos7);
111 writel(0x00002032, &s3c_qos->s3cqos8);
112
113 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
114 writel(0x80918099, &s3c_qos->s3cqos0);
115 writel(0x20410010, &s3c_qos->s3cqos1);
116 writel(0x200A2023, &s3c_qos->s3cqos2);
117 writel(0x20502001, &s3c_qos->s3cqos3);
118 writel(0x00002032, &s3c_qos->s3cqos4);
119 writel(0x20410FFF, &s3c_qos->s3cqos5);
120 writel(0x200A2023, &s3c_qos->s3cqos6);
121 writel(0x20502001, &s3c_qos->s3cqos7);
122 writel(0x20142032, &s3c_qos->s3cqos8);
123
124 /* DBSC -QoS */
125 /* DBSC0 - Read */
126 for (i = DBSC3_00; i < DBSC3_NR; i++) {
127 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
128 writel(0x00000002, &qos_addr->dblgcnt);
129 writel(0x00002096, &qos_addr->dbtmval0);
130 writel(0x00002064, &qos_addr->dbtmval1);
131 writel(0x00002032, &qos_addr->dbtmval2);
132 writel(0x00001FB0, &qos_addr->dbtmval3);
133 writel(0x00000001, &qos_addr->dbrqctr);
134 writel(0x0000204B, &qos_addr->dbthres0);
135 writel(0x0000204B, &qos_addr->dbthres1);
136 writel(0x00001FC4, &qos_addr->dbthres2);
137 writel(0x00000001, &qos_addr->dblgqon);
138 }
139
140 /* DBSC0 - Write */
141 for (i = DBSC3_00; i < DBSC3_NR; i++) {
142 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
143 writel(0x00000002, &qos_addr->dblgcnt);
144 writel(0x00002096, &qos_addr->dbtmval0);
145 writel(0x0000206E, &qos_addr->dbtmval1);
146 writel(0x00002050, &qos_addr->dbtmval2);
147 writel(0x0000203A, &qos_addr->dbtmval3);
148 writel(0x00000001, &qos_addr->dbrqctr);
149 writel(0x0000205A, &qos_addr->dbthres0);
150 writel(0x0000205A, &qos_addr->dbthres1);
151 writel(0x0000203C, &qos_addr->dbthres2);
152 writel(0x00000001, &qos_addr->dblgqon);
153 }
154
155 /* MXI -QoS */
156 /* Transaction Control (MXI) */
157 mxi = (struct rcar_mxi *)MXI_BASE;
158 writel(0x00000100, &mxi->mxaxirtcr);
159 writel(0xFF530100, &mxi->mxaxiwtcr);
160 writel(0x00000100, &mxi->mxs3crtcr);
161 writel(0xFF530100, &mxi->mxs3cwtcr);
162 writel(0x004000C0, &mxi->mxsaar0);
163 writel(0x02000800, &mxi->mxsaar1);
164
165 /* QoS Control (MXI) */
166 mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
167 writel(0x0000000C, &mxi_qos->du0);
168
169 /* AXI -QoS */
170 /* Transaction Control (MXI) */
171 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
172 writel(0x00000102, &axi_qos->qosconf);
173 writel(0x0000205F, &axi_qos->qosctset0);
174 writel(0x00000001, &axi_qos->qosreqctr);
175 writel(0x00000001, &axi_qos->qosqon);
176
177 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
178 writel(0x00000100, &axi_qos->qosconf);
179 writel(0x00002053, &axi_qos->qosctset0);
180 writel(0x00000001, &axi_qos->qosreqctr);
181 writel(0x00000001, &axi_qos->qosqon);
182 writel(0x00000005, &axi_qos->qosin);
183
184 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
185 writel(0x00000100, &axi_qos->qosconf);
186 writel(0x00002029, &axi_qos->qosctset0);
187 writel(0x00000001, &axi_qos->qosreqctr);
188 writel(0x00000001, &axi_qos->qosqon);
189 writel(0x00000005, &axi_qos->qosin);
190
191 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
192 writel(0x00000102, &axi_qos->qosconf);
193 writel(0x0000205F, &axi_qos->qosctset0);
194 writel(0x00000001, &axi_qos->qosreqctr);
195 writel(0x00000001, &axi_qos->qosqon);
196 writel(0x00000005, &axi_qos->qosin);
197
198 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
199 writel(0x00000100, &axi_qos->qosconf);
200 writel(0x00002053, &axi_qos->qosctset0);
201 writel(0x00000001, &axi_qos->qosreqctr);
202 writel(0x00000001, &axi_qos->qosqon);
203 writel(0x00000005, &axi_qos->qosin);
204
205 axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
206 writel(0x00000100, &axi_qos->qosconf);
207 writel(0x000020A6, &axi_qos->qosctset0);
208 writel(0x00000001, &axi_qos->qosreqctr);
209 writel(0x00000001, &axi_qos->qosqon);
210 writel(0x00000005, &axi_qos->qosin);
211
212 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
213 writel(0x00000100, &axi_qos->qosconf);
214 writel(0x000020A6, &axi_qos->qosctset0);
215 writel(0x00000001, &axi_qos->qosreqctr);
216 writel(0x00000001, &axi_qos->qosqon);
217 writel(0x00000005, &axi_qos->qosin);
218
219 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
220 writel(0x00000102, &axi_qos->qosconf);
221 writel(0x0000205F, &axi_qos->qosctset0);
222 writel(0x00000001, &axi_qos->qosreqctr);
223 writel(0x00000001, &axi_qos->qosqon);
224
225 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
226 writel(0x00000102, &axi_qos->qosconf);
227 writel(0x0000205F, &axi_qos->qosctset0);
228 writel(0x00000001, &axi_qos->qosreqctr);
229 writel(0x00000001, &axi_qos->qosqon);
230
231 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
232 writel(0x00000100, &axi_qos->qosconf);
233 writel(0x0000214C, &axi_qos->qosctset0);
234 writel(0x00000001, &axi_qos->qosreqctr);
235 writel(0x00000001, &axi_qos->qosqon);
236 writel(0x00000005, &axi_qos->qosin);
237
238 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
239 writel(0x00000101, &axi_qos->qosconf);
240 writel(0x00002008, &axi_qos->qosctset0);
241 writel(0x00000010, &axi_qos->qosreqctr);
242 writel(0x00000001, &axi_qos->qosqon);
243
244 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
245 writel(0x00000101, &axi_qos->qosconf);
246 writel(0x00002008, &axi_qos->qosctset0);
247 writel(0x00000010, &axi_qos->qosreqctr);
248 writel(0x00000001, &axi_qos->qosqon);
249
250 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
251 writel(0x00000101, &axi_qos->qosconf);
252 writel(0x00002008, &axi_qos->qosctset0);
253 writel(0x00000010, &axi_qos->qosreqctr);
254 writel(0x00000001, &axi_qos->qosqon);
255
256 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
257 writel(0x00000101, &axi_qos->qosconf);
258 writel(0x00002008, &axi_qos->qosctset0);
259 writel(0x00000010, &axi_qos->qosreqctr);
260 writel(0x00000001, &axi_qos->qosqon);
261
262 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
263 writel(0x00000102, &axi_qos->qosconf);
264 writel(0x0000205F, &axi_qos->qosctset0);
265 writel(0x00000001, &axi_qos->qosreqctr);
266 writel(0x00000001, &axi_qos->qosqon);
267
268 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
269 writel(0x00000000, &axi_qos->qosconf);
270 writel(0x0000214C, &axi_qos->qosctset0);
271 writel(0x00000001, &axi_qos->qosreqctr);
272 writel(0x00000001, &axi_qos->qosqon);
273
274 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
275 writel(0x00000000, &axi_qos->qosconf);
276 writel(0x0000214C, &axi_qos->qosctset0);
277 writel(0x00000001, &axi_qos->qosreqctr);
278 writel(0x00000001, &axi_qos->qosqon);
279 writel(0x00000005, &axi_qos->qosin);
280
281 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
282 writel(0x00000000, &axi_qos->qosconf);
283 writel(0x0000214C, &axi_qos->qosctset0);
284 writel(0x00000001, &axi_qos->qosreqctr);
285 writel(0x00000001, &axi_qos->qosqon);
286 writel(0x00000005, &axi_qos->qosin);
287
288 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
289 writel(0x00000000, &axi_qos->qosconf);
290 writel(0x0000214C, &axi_qos->qosctset0);
291 writel(0x00000001, &axi_qos->qosreqctr);
292 writel(0x00000001, &axi_qos->qosqon);
293 writel(0x00000005, &axi_qos->qosin);
294
295 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
296 writel(0x00000100, &axi_qos->qosconf);
297 writel(0x000020A6, &axi_qos->qosctset0);
298 writel(0x00000001, &axi_qos->qosreqctr);
299 writel(0x00000001, &axi_qos->qosqon);
300 writel(0x00000005, &axi_qos->qosin);
301
302 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADM_BASE;
303 writel(0x00000100, &axi_qos->qosconf);
304 writel(0x0000214C, &axi_qos->qosctset0);
305 writel(0x00000001, &axi_qos->qosreqctr);
306 writel(0x00000001, &axi_qos->qosqon);
307 writel(0x00000005, &axi_qos->qosin);
308
309 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADS_BASE;
310 writel(0x00000101, &axi_qos->qosconf);
311 writel(0x0000214C, &axi_qos->qosctset0);
312 writel(0x00000020, &axi_qos->qosreqctr);
313 writel(0x00000001, &axi_qos->qosqon);
314 writel(0x00000005, &axi_qos->qosin);
315
316 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX_BASE;
317 writel(0x00002041, &axi_qos->qosctset1);
318 writel(0x00002023, &axi_qos->qosctset2);
319 writel(0x0000200A, &axi_qos->qosctset3);
320 writel(0x00002050, &axi_qos->qosthres0);
321 writel(0x00002032, &axi_qos->qosthres1);
322 writel(0x00002014, &axi_qos->qosthres2);
323
324 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AXI64TO128W_BASE;
325 writel(0x00000102, &axi_qos->qosconf);
326 writel(0x0000205F, &axi_qos->qosctset0);
327 writel(0x00000001, &axi_qos->qosreqctr);
328 writel(0x00000001, &axi_qos->qosqon);
329
330 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVBW_BASE;
331 writel(0x00000100, &axi_qos->qosconf);
332 writel(0x00002053, &axi_qos->qosctset0);
333 writel(0x00000001, &axi_qos->qosreqctr);
334 writel(0x00000001, &axi_qos->qosqon);
335 writel(0x00000005, &axi_qos->qosin);
336
337 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50W_BASE;
338 writel(0x00000100, &axi_qos->qosconf);
339 writel(0x00002029, &axi_qos->qosctset0);
340 writel(0x00000001, &axi_qos->qosreqctr);
341 writel(0x00000001, &axi_qos->qosqon);
342 writel(0x00000005, &axi_qos->qosin);
343
344 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCIW_BASE;
345 writel(0x00000102, &axi_qos->qosconf);
346 writel(0x0000205F, &axi_qos->qosctset0);
347 writel(0x00000001, &axi_qos->qosreqctr);
348 writel(0x00000001, &axi_qos->qosqon);
349 writel(0x00000005, &axi_qos->qosin);
350
351 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCSW_BASE;
352 writel(0x00000100, &axi_qos->qosconf);
353 writel(0x00002053, &axi_qos->qosctset0);
354 writel(0x00000001, &axi_qos->qosreqctr);
355 writel(0x00000001, &axi_qos->qosqon);
356 writel(0x00000005, &axi_qos->qosin);
357
358 axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2DW_BASE;
359 writel(0x00000100, &axi_qos->qosconf);
360 writel(0x000020A6, &axi_qos->qosctset0);
361 writel(0x00000001, &axi_qos->qosreqctr);
362 writel(0x00000001, &axi_qos->qosqon);
363 writel(0x00000005, &axi_qos->qosin);
364
365 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0W_BASE;
366 writel(0x00000102, &axi_qos->qosconf);
367 writel(0x0000205F, &axi_qos->qosctset0);
368 writel(0x00000001, &axi_qos->qosreqctr);
369 writel(0x00000001, &axi_qos->qosqon);
370
371 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1W_BASE;
372 writel(0x00000102, &axi_qos->qosconf);
373 writel(0x0000205F, &axi_qos->qosctset0);
374 writel(0x00000001, &axi_qos->qosreqctr);
375 writel(0x00000001, &axi_qos->qosqon);
376
377 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2W_BASE;
378 writel(0x00000102, &axi_qos->qosconf);
379 writel(0x0000205F, &axi_qos->qosctset0);
380 writel(0x00000001, &axi_qos->qosreqctr);
381 writel(0x00000001, &axi_qos->qosqon);
382
383 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBSW_BASE;
384 writel(0x00000100, &axi_qos->qosconf);
385 writel(0x0000214C, &axi_qos->qosctset0);
386 writel(0x00000001, &axi_qos->qosreqctr);
387 writel(0x00000001, &axi_qos->qosqon);
388 writel(0x00000005, &axi_qos->qosin);
389
390 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTXBW_BASE;
391 writel(0x00000102, &axi_qos->qosconf);
392 writel(0x0000205F, &axi_qos->qosctset0);
393 writel(0x00000001, &axi_qos->qosreqctr);
394 writel(0x00000001, &axi_qos->qosqon);
395
396 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0W_BASE;
397 writel(0x00000000, &axi_qos->qosconf);
398 writel(0x0000214C, &axi_qos->qosctset0);
399 writel(0x00000001, &axi_qos->qosreqctr);
400 writel(0x00000001, &axi_qos->qosqon);
401 writel(0x00000005, &axi_qos->qosin);
402
403 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1W_BASE;
404 writel(0x00000000, &axi_qos->qosconf);
405 writel(0x0000214C, &axi_qos->qosctset0);
406 writel(0x00000001, &axi_qos->qosreqctr);
407 writel(0x00000001, &axi_qos->qosqon);
408 writel(0x00000005, &axi_qos->qosin);
409
410 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0W_BASE;
411 writel(0x00000000, &axi_qos->qosconf);
412 writel(0x0000214C, &axi_qos->qosctset0);
413 writel(0x00000001, &axi_qos->qosreqctr);
414 writel(0x00000001, &axi_qos->qosqon);
415 writel(0x00000005, &axi_qos->qosin);
416
417 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1W_BASE;
418 writel(0x00000000, &axi_qos->qosconf);
419 writel(0x0000214C, &axi_qos->qosctset0);
420 writel(0x00000001, &axi_qos->qosreqctr);
421 writel(0x00000001, &axi_qos->qosqon);
422 writel(0x00000005, &axi_qos->qosin);
423
424 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRABW_BASE;
425 writel(0x00000100, &axi_qos->qosconf);
426 writel(0x000020A6, &axi_qos->qosctset0);
427 writel(0x00000001, &axi_qos->qosreqctr);
428 writel(0x00000001, &axi_qos->qosqon);
429 writel(0x00000005, &axi_qos->qosin);
430
431 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADMW_BASE;
432 writel(0x00000100, &axi_qos->qosconf);
433 writel(0x0000214C, &axi_qos->qosctset0);
434 writel(0x00000001, &axi_qos->qosreqctr);
435 writel(0x00000001, &axi_qos->qosqon);
436 writel(0x00000005, &axi_qos->qosin);
437
438 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADSW_BASE;
439 writel(0x00000101, &axi_qos->qosconf);
440 writel(0x0000214C, &axi_qos->qosctset0);
441 writel(0x00000020, &axi_qos->qosreqctr);
442 writel(0x00000001, &axi_qos->qosqon);
443 writel(0x00000005, &axi_qos->qosin);
444
445 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYXW_BASE;
446 writel(0x00002041, &axi_qos->qosctset1);
447 writel(0x00002023, &axi_qos->qosctset2);
448 writel(0x0000200A, &axi_qos->qosctset3);
449 writel(0x00002050, &axi_qos->qosthres0);
450 writel(0x00002032, &axi_qos->qosthres1);
451 writel(0x00002014, &axi_qos->qosthres2);
452
453 /* QoS Register (SYS-AXI256) */
454 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
455 writel(0x00000102, &axi_qos->qosconf);
456 writel(0x0000205F, &axi_qos->qosctset0);
457 writel(0x00000001, &axi_qos->qosreqctr);
458 writel(0x00000001, &axi_qos->qosqon);
459
460 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI_BASE;
461 writel(0x00000102, &axi_qos->qosconf);
462 writel(0x0000205F, &axi_qos->qosctset0);
463 writel(0x00000001, &axi_qos->qosreqctr);
464 writel(0x00000001, &axi_qos->qosqon);
465
466 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
467 writel(0x00000102, &axi_qos->qosconf);
468 writel(0x0000205F, &axi_qos->qosctset0);
469 writel(0x00000001, &axi_qos->qosreqctr);
470 writel(0x00000001, &axi_qos->qosqon);
471
472 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0_BASE;
473 writel(0x00000100, &axi_qos->qosconf);
474 writel(0x0000211B, &axi_qos->qosctset0);
475 writel(0x00000001, &axi_qos->qosreqctr);
476 writel(0x00000001, &axi_qos->qosqon);
477 writel(0x00000005, &axi_qos->qosin);
478
479 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2_BASE;
480 writel(0x00002041, &axi_qos->qosctset1);
481 writel(0x00002023, &axi_qos->qosctset2);
482 writel(0x0000200A, &axi_qos->qosctset3);
483 writel(0x00002050, &axi_qos->qosthres0);
484 writel(0x00002032, &axi_qos->qosthres1);
485 writel(0x00002014, &axi_qos->qosthres2);
486
487 axi_qos = (struct rcar_axi_qos *)SYS_AXI256W_AXI128TO256_BASE;
488 writel(0x00000102, &axi_qos->qosconf);
489 writel(0x0000205F, &axi_qos->qosctset0);
490 writel(0x00000001, &axi_qos->qosreqctr);
491 writel(0x00000001, &axi_qos->qosqon);
492
493 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXMW_BASE;
494 writel(0x00000102, &axi_qos->qosconf);
495 writel(0x0000205F, &axi_qos->qosctset0);
496 writel(0x00000001, &axi_qos->qosreqctr);
497 writel(0x00000001, &axi_qos->qosqon);
498
499 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXIW_BASE;
500 writel(0x00000102, &axi_qos->qosconf);
501 writel(0x0000205F, &axi_qos->qosctset0);
502 writel(0x00000001, &axi_qos->qosreqctr);
503 writel(0x00000001, &axi_qos->qosqon);
504
505 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0W_BASE;
506 writel(0x00000100, &axi_qos->qosconf);
507 writel(0x00002029, &axi_qos->qosctset0);
508 writel(0x00000001, &axi_qos->qosreqctr);
509 writel(0x00000001, &axi_qos->qosqon);
510 writel(0x00000005, &axi_qos->qosin);
511
512 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2W_BASE;
513 writel(0x00002041, &axi_qos->qosctset1);
514 writel(0x00002023, &axi_qos->qosctset2);
515 writel(0x0000200A, &axi_qos->qosctset3);
516 writel(0x00002050, &axi_qos->qosthres0);
517 writel(0x00002032, &axi_qos->qosthres1);
518 writel(0x00002014, &axi_qos->qosthres2);
519
520 /* QoS Register (RT-AXI) */
521 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
522 writel(0x00000000, &axi_qos->qosconf);
523 writel(0x00002055, &axi_qos->qosctset0);
524 writel(0x00000000, &axi_qos->qosreqctr);
525 writel(0x00000000, &axi_qos->qosqon);
526
527 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
528 writel(0x00000000, &axi_qos->qosconf);
529 writel(0x00002055, &axi_qos->qosctset0);
530 writel(0x00000000, &axi_qos->qosreqctr);
531 writel(0x00000000, &axi_qos->qosqon);
532
533 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
534 writel(0x00000000, &axi_qos->qosconf);
535 writel(0x00002001, &axi_qos->qosctset0);
536 writel(0x00000000, &axi_qos->qosreqctr);
537 writel(0x00000000, &axi_qos->qosqon);
538
539 axi_qos = (struct rcar_axi_qos *)RT_AXI_RT_BASE;
540 writel(0x00002001, &axi_qos->qosctset1);
541 writel(0x00002001, &axi_qos->qosctset2);
542 writel(0x00002001, &axi_qos->qosctset3);
543 writel(0x00000000, &axi_qos->qosthres0);
544 writel(0x00000000, &axi_qos->qosthres1);
545 writel(0x00000000, &axi_qos->qosthres2);
546
547 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHXW_BASE;
548 writel(0x00000000, &axi_qos->qosconf);
549 writel(0x00002055, &axi_qos->qosctset0);
550 writel(0x00000000, &axi_qos->qosreqctr);
551 writel(0x00000000, &axi_qos->qosqon);
552
553 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBGW_BASE;
554 writel(0x00000000, &axi_qos->qosconf);
555 writel(0x00002055, &axi_qos->qosctset0);
556 writel(0x00000000, &axi_qos->qosreqctr);
557 writel(0x00000000, &axi_qos->qosqon);
558
559 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128W_BASE;
560 writel(0x00000000, &axi_qos->qosconf);
561 writel(0x00002001, &axi_qos->qosctset0);
562 writel(0x00000000, &axi_qos->qosreqctr);
563 writel(0x00000000, &axi_qos->qosqon);
564
565 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTW_BASE;
566 writel(0x00002001, &axi_qos->qosctset1);
567 writel(0x00002001, &axi_qos->qosctset2);
568 writel(0x00002001, &axi_qos->qosctset3);
569 writel(0x00000000, &axi_qos->qosthres0);
570 writel(0x00000000, &axi_qos->qosthres1);
571 writel(0x00000000, &axi_qos->qosthres2);
572
573 /* QoS Register (CCI-AXI) */
574 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
575 writel(0x00000101, &axi_qos->qosconf);
576 writel(0x00002008, &axi_qos->qosctset0);
577 writel(0x00002041, &axi_qos->qosctset1);
578 writel(0x00002023, &axi_qos->qosctset2);
579 writel(0x0000200A, &axi_qos->qosctset3);
580 writel(0x00000010, &axi_qos->qosreqctr);
581 writel(0x00002050, &axi_qos->qosthres0);
582 writel(0x00002032, &axi_qos->qosthres1);
583 writel(0x00002014, &axi_qos->qosthres2);
584 writel(0x00000001, &axi_qos->qosqon);
585
586 axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
587 writel(0x00000102, &axi_qos->qosconf);
588 writel(0x0000205F, &axi_qos->qosctset0);
589 writel(0x00002041, &axi_qos->qosctset1);
590 writel(0x00002023, &axi_qos->qosctset2);
591 writel(0x0000200A, &axi_qos->qosctset3);
592 writel(0x00000001, &axi_qos->qosreqctr);
593 writel(0x00002050, &axi_qos->qosthres0);
594 writel(0x00002032, &axi_qos->qosthres1);
595 writel(0x00002014, &axi_qos->qosthres2);
596 writel(0x00000001, &axi_qos->qosqon);
597
598 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
599 writel(0x00000101, &axi_qos->qosconf);
600 writel(0x00002008, &axi_qos->qosctset0);
601 writel(0x00002041, &axi_qos->qosctset1);
602 writel(0x00002023, &axi_qos->qosctset2);
603 writel(0x0000000A, &axi_qos->qosctset3);
604 writel(0x00000010, &axi_qos->qosreqctr);
605 writel(0x00002050, &axi_qos->qosthres0);
606 writel(0x00002032, &axi_qos->qosthres1);
607 writel(0x00002018, &axi_qos->qosthres2);
608 writel(0x00000001, &axi_qos->qosqon);
609
610 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
611 writel(0x00000101, &axi_qos->qosconf);
612 writel(0x00002008, &axi_qos->qosctset0);
613 writel(0x00002041, &axi_qos->qosctset1);
614 writel(0x00002023, &axi_qos->qosctset2);
615 writel(0x0000200A, &axi_qos->qosctset3);
616 writel(0x00000010, &axi_qos->qosreqctr);
617 writel(0x00002050, &axi_qos->qosthres0);
618 writel(0x00002032, &axi_qos->qosthres1);
619 writel(0x00002014, &axi_qos->qosthres2);
620 writel(0x00000001, &axi_qos->qosqon);
621
622 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
623 writel(0x00000101, &axi_qos->qosconf);
624 writel(0x00002008, &axi_qos->qosctset0);
625 writel(0x00002041, &axi_qos->qosctset1);
626 writel(0x00002023, &axi_qos->qosctset2);
627 writel(0x0000200A, &axi_qos->qosctset3);
628 writel(0x00000010, &axi_qos->qosreqctr);
629 writel(0x00002050, &axi_qos->qosthres0);
630 writel(0x00002032, &axi_qos->qosthres1);
631 writel(0x00002014, &axi_qos->qosthres2);
632 writel(0x00000001, &axi_qos->qosqon);
633
634 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
635 writel(0x00000102, &axi_qos->qosconf);
636 writel(0x0000205F, &axi_qos->qosctset0);
637 writel(0x00002041, &axi_qos->qosctset1);
638 writel(0x00002023, &axi_qos->qosctset2);
639 writel(0x0000200A, &axi_qos->qosctset3);
640 writel(0x00000001, &axi_qos->qosreqctr);
641 writel(0x00002050, &axi_qos->qosthres0);
642 writel(0x00002032, &axi_qos->qosthres1);
643 writel(0x00002014, &axi_qos->qosthres2);
644 writel(0x00000001, &axi_qos->qosqon);
645
646 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
647 writel(0x00000101, &axi_qos->qosconf);
648 writel(0x00002008, &axi_qos->qosctset0);
649 writel(0x00002041, &axi_qos->qosctset1);
650 writel(0x00002023, &axi_qos->qosctset2);
651 writel(0x0000200A, &axi_qos->qosctset3);
652 writel(0x00000001, &axi_qos->qosreqctr);
653 writel(0x00002050, &axi_qos->qosthres0);
654 writel(0x00002032, &axi_qos->qosthres1);
655 writel(0x00002014, &axi_qos->qosthres2);
656 writel(0x00000001, &axi_qos->qosqon);
657
658 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
659 writel(0x00000101, &axi_qos->qosconf);
660 writel(0x00002008, &axi_qos->qosctset0);
661 writel(0x00002041, &axi_qos->qosctset1);
662 writel(0x00002023, &axi_qos->qosctset2);
663 writel(0x0000200A, &axi_qos->qosctset3);
664 writel(0x00000010, &axi_qos->qosreqctr);
665 writel(0x00002050, &axi_qos->qosthres0);
666 writel(0x00002032, &axi_qos->qosthres1);
667 writel(0x00002014, &axi_qos->qosthres2);
668 writel(0x00000001, &axi_qos->qosqon);
669
670 /* QoS Register (Media-AXI) */
671 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
672 writel(0x00000102, &axi_qos->qosconf);
673 writel(0x000020DC, &axi_qos->qosctset0);
674 writel(0x00002096, &axi_qos->qosctset1);
675 writel(0x00002030, &axi_qos->qosctset2);
676 writel(0x00002030, &axi_qos->qosctset3);
677 writel(0x00000020, &axi_qos->qosreqctr);
678 writel(0x000020AA, &axi_qos->qosthres0);
679 writel(0x00002032, &axi_qos->qosthres1);
680 writel(0x00000001, &axi_qos->qosthres2);
681
682 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
683 writel(0x00000102, &axi_qos->qosconf);
684 writel(0x000020DC, &axi_qos->qosctset0);
685 writel(0x00002096, &axi_qos->qosctset1);
686 writel(0x00002030, &axi_qos->qosctset2);
687 writel(0x00002030, &axi_qos->qosctset3);
688 writel(0x00000020, &axi_qos->qosreqctr);
689 writel(0x000020AA, &axi_qos->qosthres0);
690 writel(0x00002032, &axi_qos->qosthres1);
691 writel(0x00000001, &axi_qos->qosthres2);
692
693 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
694 writel(0x00000001, &axi_qos->qosconf);
695 writel(0x00002018, &axi_qos->qosctset0);
696 writel(0x00000020, &axi_qos->qosreqctr);
697 writel(0x00002006, &axi_qos->qosthres0);
698 writel(0x00002001, &axi_qos->qosthres1);
699 writel(0x00000001, &axi_qos->qosthres2);
700 writel(0x00000001, &axi_qos->qosqon);
701
702 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
703 writel(0x00000100, &axi_qos->qosconf);
704 writel(0x00002259, &axi_qos->qosctset0);
705 writel(0x00000001, &axi_qos->qosreqctr);
706 writel(0x00002050, &axi_qos->qosthres0);
707 writel(0x00002032, &axi_qos->qosthres1);
708 writel(0x00002014, &axi_qos->qosthres2);
709 writel(0x00000001, &axi_qos->qosqon);
710
711 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0R_BASE;
712 writel(0x00000100, &axi_qos->qosconf);
713 writel(0x00002053, &axi_qos->qosctset0);
714 writel(0x00000001, &axi_qos->qosreqctr);
715 writel(0x00002050, &axi_qos->qosthres0);
716 writel(0x00002032, &axi_qos->qosthres1);
717 writel(0x00002014, &axi_qos->qosthres2);
718 writel(0x00000001, &axi_qos->qosqon);
719
720 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0W_BASE;
721 writel(0x00000100, &axi_qos->qosconf);
722 writel(0x00002053, &axi_qos->qosctset0);
723 writel(0x00000001, &axi_qos->qosreqctr);
724 writel(0x00002050, &axi_qos->qosthres0);
725 writel(0x00002032, &axi_qos->qosthres1);
726 writel(0x00002014, &axi_qos->qosthres2);
727 writel(0x00000001, &axi_qos->qosqon);
728
729 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0R_BASE;
730 writel(0x00000100, &axi_qos->qosconf);
731 writel(0x00002053, &axi_qos->qosctset0);
732 writel(0x00000001, &axi_qos->qosreqctr);
733 writel(0x00002050, &axi_qos->qosthres0);
734 writel(0x00002032, &axi_qos->qosthres1);
735 writel(0x00002014, &axi_qos->qosthres2);
736 writel(0x00000001, &axi_qos->qosqon);
737
738 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0W_BASE;
739 writel(0x00000100, &axi_qos->qosconf);
740 writel(0x00002053, &axi_qos->qosctset0);
741 writel(0x00000001, &axi_qos->qosreqctr);
742 writel(0x00002050, &axi_qos->qosthres0);
743 writel(0x00002032, &axi_qos->qosthres1);
744 writel(0x00002014, &axi_qos->qosthres2);
745 writel(0x00000001, &axi_qos->qosqon);
746
747 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1R_BASE;
748 writel(0x00000100, &axi_qos->qosconf);
749 writel(0x00002053, &axi_qos->qosctset0);
750 writel(0x00000001, &axi_qos->qosreqctr);
751 writel(0x00002050, &axi_qos->qosthres0);
752 writel(0x00002032, &axi_qos->qosthres1);
753 writel(0x00002014, &axi_qos->qosthres2);
754 writel(0x00000001, &axi_qos->qosqon);
755
756 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1W_BASE;
757 writel(0x00000100, &axi_qos->qosconf);
758 writel(0x00002053, &axi_qos->qosctset0);
759 writel(0x00000001, &axi_qos->qosreqctr);
760 writel(0x00002050, &axi_qos->qosthres0);
761 writel(0x00002032, &axi_qos->qosthres1);
762 writel(0x00002014, &axi_qos->qosthres2);
763 writel(0x00000001, &axi_qos->qosqon);
764
765 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
766 writel(0x00000101, &axi_qos->qosconf);
767 writel(0x00002046, &axi_qos->qosctset0);
768 writel(0x00000020, &axi_qos->qosreqctr);
769 writel(0x00002050, &axi_qos->qosthres0);
770 writel(0x00002032, &axi_qos->qosthres1);
771 writel(0x00002014, &axi_qos->qosthres2);
772 writel(0x00000001, &axi_qos->qosqon);
773
774 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN1W_BASE;
775 writel(0x00000101, &axi_qos->qosconf);
776 writel(0x00002046, &axi_qos->qosctset0);
777 writel(0x00000020, &axi_qos->qosreqctr);
778 writel(0x00002050, &axi_qos->qosthres0);
779 writel(0x00002032, &axi_qos->qosthres1);
780 writel(0x00002014, &axi_qos->qosthres2);
781 writel(0x00000001, &axi_qos->qosqon);
782
783 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_RDRW_BASE;
784 writel(0x00000101, &axi_qos->qosconf);
785 writel(0x000020D0, &axi_qos->qosctset0);
786 writel(0x00000020, &axi_qos->qosreqctr);
787 writel(0x00002050, &axi_qos->qosthres0);
788 writel(0x00002032, &axi_qos->qosthres1);
789 writel(0x00002014, &axi_qos->qosthres2);
790 writel(0x00000001, &axi_qos->qosqon);
791
792 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01R_BASE;
793 writel(0x00000101, &axi_qos->qosconf);
794 writel(0x00002034, &axi_qos->qosctset0);
795 writel(0x0000000C, &axi_qos->qosreqctr);
796 writel(0x00002050, &axi_qos->qosthres0);
797 writel(0x00002032, &axi_qos->qosthres1);
798 writel(0x00002014, &axi_qos->qosthres2);
799 writel(0x00000001, &axi_qos->qosqon);
800
801 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01W_BASE;
802 writel(0x00000101, &axi_qos->qosconf);
803 writel(0x0000200D, &axi_qos->qosctset0);
804 writel(0x000000C0, &axi_qos->qosreqctr);
805 writel(0x00002050, &axi_qos->qosthres0);
806 writel(0x00002032, &axi_qos->qosthres1);
807 writel(0x00002014, &axi_qos->qosthres2);
808 writel(0x00000001, &axi_qos->qosqon);
809
810 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23R_BASE;
811 writel(0x00000101, &axi_qos->qosconf);
812 writel(0x00002034, &axi_qos->qosctset0);
813 writel(0x0000000C, &axi_qos->qosreqctr);
814 writel(0x00002050, &axi_qos->qosthres0);
815 writel(0x00002032, &axi_qos->qosthres1);
816 writel(0x00002014, &axi_qos->qosthres2);
817 writel(0x00000001, &axi_qos->qosqon);
818
819 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23W_BASE;
820 writel(0x00000101, &axi_qos->qosconf);
821 writel(0x0000200D, &axi_qos->qosctset0);
822 writel(0x000000C0, &axi_qos->qosreqctr);
823 writel(0x00002050, &axi_qos->qosthres0);
824 writel(0x00002032, &axi_qos->qosthres1);
825 writel(0x00002014, &axi_qos->qosthres2);
826 writel(0x00000001, &axi_qos->qosqon);
827
828 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45R_BASE;
829 writel(0x00000101, &axi_qos->qosconf);
830 writel(0x00002034, &axi_qos->qosctset0);
831 writel(0x0000000C, &axi_qos->qosreqctr);
832 writel(0x00002050, &axi_qos->qosthres0);
833 writel(0x00002032, &axi_qos->qosthres1);
834 writel(0x00002014, &axi_qos->qosthres2);
835 writel(0x00000001, &axi_qos->qosqon);
836
837 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45W_BASE;
838 writel(0x00000101, &axi_qos->qosconf);
839 writel(0x0000200D, &axi_qos->qosctset0);
840 writel(0x000000C0, &axi_qos->qosreqctr);
841 writel(0x00002050, &axi_qos->qosthres0);
842 writel(0x00002032, &axi_qos->qosthres1);
843 writel(0x00002014, &axi_qos->qosthres2);
844 writel(0x00000001, &axi_qos->qosqon);
845
846 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
847 writel(0x00000100, &axi_qos->qosconf);
848 writel(0x00002069, &axi_qos->qosctset0);
849 writel(0x00000001, &axi_qos->qosreqctr);
850 writel(0x00002050, &axi_qos->qosthres0);
851 writel(0x00002032, &axi_qos->qosthres1);
852 writel(0x00002014, &axi_qos->qosthres2);
853 writel(0x00000001, &axi_qos->qosqon);
854
855 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
856 writel(0x00000100, &axi_qos->qosconf);
857 writel(0x00002069, &axi_qos->qosctset0);
858 writel(0x00000001, &axi_qos->qosreqctr);
859 writel(0x00002050, &axi_qos->qosthres0);
860 writel(0x00002032, &axi_qos->qosthres1);
861 writel(0x00002014, &axi_qos->qosthres2);
862 writel(0x00000001, &axi_qos->qosqon);
863
864 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4R_BASE;
865 writel(0x00000100, &axi_qos->qosconf);
866 writel(0x0000204C, &axi_qos->qosctset0);
867 writel(0x00000001, &axi_qos->qosreqctr);
868 writel(0x00002050, &axi_qos->qosthres0);
869 writel(0x00002032, &axi_qos->qosthres1);
870 writel(0x00002014, &axi_qos->qosthres2);
871 writel(0x00000001, &axi_qos->qosqon);
872
873 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4W_BASE;
874 writel(0x00000100, &axi_qos->qosconf);
875 writel(0x00002200, &axi_qos->qosctset0);
876 writel(0x00000001, &axi_qos->qosreqctr);
877 writel(0x00002050, &axi_qos->qosthres0);
878 writel(0x00002032, &axi_qos->qosthres1);
879 writel(0x00002014, &axi_qos->qosthres2);
880 writel(0x00000001, &axi_qos->qosqon);
881
882 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4R_BASE;
883 writel(0x00000100, &axi_qos->qosconf);
884 writel(0x00002455, &axi_qos->qosctset0);
885 writel(0x00000001, &axi_qos->qosreqctr);
886 writel(0x00002050, &axi_qos->qosthres0);
887 writel(0x00002032, &axi_qos->qosthres1);
888 writel(0x00002014, &axi_qos->qosthres2);
889 writel(0x00000001, &axi_qos->qosqon);
890
891 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4W_BASE;
892 writel(0x00000100, &axi_qos->qosconf);
893 writel(0x00002455, &axi_qos->qosctset0);
894 writel(0x00000001, &axi_qos->qosreqctr);
895 writel(0x00002050, &axi_qos->qosthres0);
896 writel(0x00002032, &axi_qos->qosthres1);
897 writel(0x00002014, &axi_qos->qosthres2);
898 writel(0x00000001, &axi_qos->qosqon);
899
900 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
901 writel(0x00000101, &axi_qos->qosconf);
902 writel(0x00002034, &axi_qos->qosctset0);
903 writel(0x00000008, &axi_qos->qosreqctr);
904 writel(0x00002050, &axi_qos->qosthres0);
905 writel(0x00002032, &axi_qos->qosthres1);
906 writel(0x00002014, &axi_qos->qosthres2);
907 writel(0x00000001, &axi_qos->qosqon);
908
909 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
910 writel(0x00000101, &axi_qos->qosconf);
911 writel(0x000020D3, &axi_qos->qosctset0);
912 writel(0x00000008, &axi_qos->qosreqctr);
913 writel(0x00002050, &axi_qos->qosthres0);
914 writel(0x00002032, &axi_qos->qosthres1);
915 writel(0x00002014, &axi_qos->qosthres2);
916 writel(0x00000001, &axi_qos->qosqon);
917
918 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
919 writel(0x00000101, &axi_qos->qosconf);
920 writel(0x00002034, &axi_qos->qosctset0);
921 writel(0x00000008, &axi_qos->qosreqctr);
922 writel(0x00002050, &axi_qos->qosthres0);
923 writel(0x00002032, &axi_qos->qosthres1);
924 writel(0x00002014, &axi_qos->qosthres2);
925 writel(0x00000001, &axi_qos->qosqon);
926
927 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
928 writel(0x00000101, &axi_qos->qosconf);
929 writel(0x000020D3, &axi_qos->qosctset0);
930 writel(0x00000008, &axi_qos->qosreqctr);
931 writel(0x00002050, &axi_qos->qosthres0);
932 writel(0x00002032, &axi_qos->qosthres1);
933 writel(0x00002014, &axi_qos->qosthres2);
934 writel(0x00000001, &axi_qos->qosqon);
935
936 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
937 writel(0x00000101, &axi_qos->qosconf);
938 writel(0x0000201A, &axi_qos->qosctset0);
939 writel(0x00000018, &axi_qos->qosreqctr);
940 writel(0x00002050, &axi_qos->qosthres0);
941 writel(0x00002032, &axi_qos->qosthres1);
942 writel(0x00002014, &axi_qos->qosthres2);
943 writel(0x00000001, &axi_qos->qosqon);
944
945 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
946 writel(0x00000101, &axi_qos->qosconf);
947 writel(0x00002006, &axi_qos->qosctset0);
948 writel(0x00000018, &axi_qos->qosreqctr);
949 writel(0x00002050, &axi_qos->qosthres0);
950 writel(0x00002032, &axi_qos->qosthres1);
951 writel(0x00002014, &axi_qos->qosthres2);
952 writel(0x00000001, &axi_qos->qosqon);
953
954 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
955 writel(0x00000100, &axi_qos->qosconf);
956 writel(0x0000201A, &axi_qos->qosctset0);
957 writel(0x00000001, &axi_qos->qosreqctr);
958 writel(0x00002050, &axi_qos->qosthres0);
959 writel(0x00002032, &axi_qos->qosthres1);
960 writel(0x00002014, &axi_qos->qosthres2);
961 writel(0x00000001, &axi_qos->qosqon);
962
963 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
964 writel(0x00000100, &axi_qos->qosconf);
965 writel(0x00002042, &axi_qos->qosctset0);
966 writel(0x00000001, &axi_qos->qosreqctr);
967 writel(0x00002050, &axi_qos->qosthres0);
968 writel(0x00002032, &axi_qos->qosthres1);
969 writel(0x00002014, &axi_qos->qosthres2);
970 writel(0x00000001, &axi_qos->qosqon);
971
972 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0R_BASE;
973 writel(0x00000100, &axi_qos->qosconf);
974 writel(0x0000204C, &axi_qos->qosctset0);
975 writel(0x00000001, &axi_qos->qosreqctr);
976 writel(0x00002050, &axi_qos->qosthres0);
977 writel(0x00002032, &axi_qos->qosthres1);
978 writel(0x00002014, &axi_qos->qosthres2);
979 writel(0x00000001, &axi_qos->qosqon);
980
981 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0W_BASE;
982 writel(0x00000100, &axi_qos->qosconf);
983 writel(0x00002200, &axi_qos->qosctset0);
984 writel(0x00000001, &axi_qos->qosreqctr);
985 writel(0x00002050, &axi_qos->qosthres0);
986 writel(0x00002032, &axi_qos->qosthres1);
987 writel(0x00002014, &axi_qos->qosthres2);
988 writel(0x00000001, &axi_qos->qosqon);
989
990 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0R_BASE;
991 writel(0x00000100, &axi_qos->qosconf);
992 writel(0x00002455, &axi_qos->qosctset0);
993 writel(0x00000001, &axi_qos->qosreqctr);
994 writel(0x00002050, &axi_qos->qosthres0);
995 writel(0x00002032, &axi_qos->qosthres1);
996 writel(0x00002014, &axi_qos->qosthres2);
997 writel(0x00000001, &axi_qos->qosqon);
998
999 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0W_BASE;
1000 writel(0x00000100, &axi_qos->qosconf);
1001 writel(0x00002455, &axi_qos->qosctset0);
1002 writel(0x00000001, &axi_qos->qosreqctr);
1003 writel(0x00002050, &axi_qos->qosthres0);
1004 writel(0x00002032, &axi_qos->qosthres1);
1005 writel(0x00002014, &axi_qos->qosthres2);
1006 writel(0x00000001, &axi_qos->qosqon);
1007
1008 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1R_BASE;
1009 writel(0x00000100, &axi_qos->qosconf);
1010 writel(0x0000204C, &axi_qos->qosctset0);
1011 writel(0x00000001, &axi_qos->qosreqctr);
1012 writel(0x00002050, &axi_qos->qosthres0);
1013 writel(0x00002032, &axi_qos->qosthres1);
1014 writel(0x00002014, &axi_qos->qosthres2);
1015 writel(0x00000001, &axi_qos->qosqon);
1016
1017 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1W_BASE;
1018 writel(0x00000100, &axi_qos->qosconf);
1019 writel(0x00002200, &axi_qos->qosctset0);
1020 writel(0x00000001, &axi_qos->qosreqctr);
1021 writel(0x00002050, &axi_qos->qosthres0);
1022 writel(0x00002032, &axi_qos->qosthres1);
1023 writel(0x00002014, &axi_qos->qosthres2);
1024 writel(0x00000001, &axi_qos->qosqon);
1025
1026 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1R_BASE;
1027 writel(0x00000100, &axi_qos->qosconf);
1028 writel(0x00002455, &axi_qos->qosctset0);
1029 writel(0x00000001, &axi_qos->qosreqctr);
1030 writel(0x00002050, &axi_qos->qosthres0);
1031 writel(0x00002032, &axi_qos->qosthres1);
1032 writel(0x00002014, &axi_qos->qosthres2);
1033 writel(0x00000001, &axi_qos->qosqon);
1034
1035 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1W_BASE;
1036 writel(0x00000100, &axi_qos->qosconf);
1037 writel(0x00002455, &axi_qos->qosctset0);
1038 writel(0x00000001, &axi_qos->qosreqctr);
1039 writel(0x00002050, &axi_qos->qosthres0);
1040 writel(0x00002032, &axi_qos->qosthres1);
1041 writel(0x00002014, &axi_qos->qosthres2);
1042 writel(0x00000001, &axi_qos->qosqon);
1043
1044 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2R_BASE;
1045 writel(0x00000100, &axi_qos->qosconf);
1046 writel(0x0000204C, &axi_qos->qosctset0);
1047 writel(0x00000001, &axi_qos->qosreqctr);
1048 writel(0x00002050, &axi_qos->qosthres0);
1049 writel(0x00002032, &axi_qos->qosthres1);
1050 writel(0x00002014, &axi_qos->qosthres2);
1051 writel(0x00000001, &axi_qos->qosqon);
1052
1053 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2W_BASE;
1054 writel(0x00000100, &axi_qos->qosconf);
1055 writel(0x00002200, &axi_qos->qosctset0);
1056 writel(0x00000001, &axi_qos->qosreqctr);
1057 writel(0x00002050, &axi_qos->qosthres0);
1058 writel(0x00002032, &axi_qos->qosthres1);
1059 writel(0x00002014, &axi_qos->qosthres2);
1060 writel(0x00000001, &axi_qos->qosqon);
1061
1062 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2R_BASE;
1063 writel(0x00000100, &axi_qos->qosconf);
1064 writel(0x00002455, &axi_qos->qosctset0);
1065 writel(0x00000001, &axi_qos->qosreqctr);
1066 writel(0x00002050, &axi_qos->qosthres0);
1067 writel(0x00002032, &axi_qos->qosthres1);
1068 writel(0x00002014, &axi_qos->qosthres2);
1069 writel(0x00000001, &axi_qos->qosqon);
1070
1071 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2W_BASE;
1072 writel(0x00000100, &axi_qos->qosconf);
1073 writel(0x00002455, &axi_qos->qosctset0);
1074 writel(0x00000001, &axi_qos->qosreqctr);
1075 writel(0x00002050, &axi_qos->qosthres0);
1076 writel(0x00002032, &axi_qos->qosthres1);
1077 writel(0x00002014, &axi_qos->qosthres2);
1078 writel(0x00000001, &axi_qos->qosqon);
1079
1080 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3R_BASE;
1081 writel(0x00000100, &axi_qos->qosconf);
1082 writel(0x0000204C, &axi_qos->qosctset0);
1083 writel(0x00000001, &axi_qos->qosreqctr);
1084 writel(0x00002050, &axi_qos->qosthres0);
1085 writel(0x00002032, &axi_qos->qosthres1);
1086 writel(0x00002014, &axi_qos->qosthres2);
1087 writel(0x00000001, &axi_qos->qosqon);
1088
1089 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3W_BASE;
1090 writel(0x00000100, &axi_qos->qosconf);
1091 writel(0x00002200, &axi_qos->qosctset0);
1092 writel(0x00000001, &axi_qos->qosreqctr);
1093 writel(0x00002050, &axi_qos->qosthres0);
1094 writel(0x00002032, &axi_qos->qosthres1);
1095 writel(0x00002014, &axi_qos->qosthres2);
1096 writel(0x00000001, &axi_qos->qosqon);
1097
1098 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3R_BASE;
1099 writel(0x00000100, &axi_qos->qosconf);
1100 writel(0x00002455, &axi_qos->qosctset0);
1101 writel(0x00000001, &axi_qos->qosreqctr);
1102 writel(0x00002050, &axi_qos->qosthres0);
1103 writel(0x00002032, &axi_qos->qosthres1);
1104 writel(0x00002014, &axi_qos->qosthres2);
1105 writel(0x00000001, &axi_qos->qosqon);
1106
1107 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3W_BASE;
1108 writel(0x00000100, &axi_qos->qosconf);
1109 writel(0x00002455, &axi_qos->qosctset0);
1110 writel(0x00000001, &axi_qos->qosreqctr);
1111 writel(0x00002050, &axi_qos->qosthres0);
1112 writel(0x00002032, &axi_qos->qosthres1);
1113 writel(0x00002014, &axi_qos->qosthres2);
1114 writel(0x00000001, &axi_qos->qosqon);
1115
1116 /* DMS Register(SYS-AXI) */
1117 writel(0x00000000, SYS_AXI_AVBDMSCR);
1118 writel(0x00000000, SYS_AXI_AX2MDMSCR);
1119 writel(0x00000000, SYS_AXI_CC50DMSCR);
1120 writel(0x00000000, SYS_AXI_CCIDMSCR);
1121 writel(0x00000000, SYS_AXI_CSDMSCR);
1122 writel(0x00000000, SYS_AXI_G2DDMSCR);
1123 writel(0x00000000, SYS_AXI_IMP1DMSCR);
1124 writel(0x00000000, SYS_AXI_LBSMDMSCR);
1125 writel(0x00000000, SYS_AXI_MMUDSDMSCR);
1126 writel(0x00000000, SYS_AXI_MMUMXDMSCR);
1127 writel(0x00000000, SYS_AXI_MMUS0DMSCR);
1128 writel(0x00000000, SYS_AXI_MMUS1DMSCR);
1129 writel(0x00000000, SYS_AXI_RTMXDMSCR);
1130 writel(0x00000000, SYS_AXI_SDM0DMSCR);
1131 writel(0x00000000, SYS_AXI_SDM1DMSCR);
1132 writel(0x00000000, SYS_AXI_SDS0DMSCR);
1133 writel(0x00000000, SYS_AXI_SDS1DMSCR);
1134 writel(0x00000000, SYS_AXI_TRABDMSCR);
1135 writel(0x00000000, SYS_AXI_X128TO64SLVDMSCR);
1136 writel(0x00000000, SYS_AXI_X64TO128SLVDMSCR);
1137 writel(0x00000000, SYS_AXI_AVBSLVDMSCR);
1138 writel(0x00000000, SYS_AXI_AX2SLVDMSCR);
1139 writel(0x00000000, SYS_AXI_GICSLVDMSCR);
1140 writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
1141 writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
1142 writel(0x00000000, SYS_AXI_IMX0SLVDMSCR);
1143 writel(0x00000000, SYS_AXI_IMX1SLVDMSCR);
1144 writel(0x00000000, SYS_AXI_IMX2SLVDMSCR);
1145 writel(0x00000000, SYS_AXI_LBSSLVDMSCR);
1146 writel(0x00000000, SYS_AXI_MXTSLVDMSCR);
1147 writel(0x00000000, SYS_AXI_SYAPBSLVDMSCR);
1148 writel(0x00000000, SYS_AXI_QSAPBSLVDMSCR);
1149 writel(0x00000000, SYS_AXI_RTXSLVDMSCR);
1150 writel(0x00000000, SYS_AXI_SAPC1SLVDMSCR);
1151 writel(0x00000000, SYS_AXI_SAPC2SLVDMSCR);
1152 writel(0x00000000, SYS_AXI_SAPC3SLVDMSCR);
1153 writel(0x00000000, SYS_AXI_SAPC65SLVDMSCR);
1154 writel(0x00000000, SYS_AXI_SAPC8SLVDMSCR);
1155 writel(0x00000000, SYS_AXI_SDAP0SLVDMSCR);
1156 writel(0x00000000, SYS_AXI_SGXSLV1SLVDMSCR);
1157 writel(0x00000000, SYS_AXI_STBSLVDMSCR);
1158 writel(0x00000000, SYS_AXI_STMSLVDMSCR);
1159 writel(0x00000000, SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR);
1160 writel(0x00000000, SYS_AXI_TSPL0SLVDMSCR);
1161 writel(0x00000000, SYS_AXI_TSPL1SLVDMSCR);
1162 writel(0x00000000, SYS_AXI_TSPL2SLVDMSCR);
1163 writel(0x00000000, SYS_AXI_UTLBDSSLVDMSCR);
1164 writel(0x00000000, SYS_AXI_UTLBS0SLVDMSCR);
1165 writel(0x00000000, SYS_AXI_UTLBS1SLVDMSCR);
1166 writel(0x00000000, SYS_AXI_ROT0DMSCR);
1167 writel(0x00000000, SYS_AXI_ROT1DMSCR);
1168 writel(0x00000000, SYS_AXI_ROT2DMSCR);
1169 writel(0x00000000, SYS_AXI_ROT3DMSCR);
1170 writel(0x00000000, SYS_AXI_ROT4DMSCR);
1171 writel(0x00000000, SYS_AXI_IMUX3SLVDMSCR);
1172 writel(0x00000000, SYS_AXI_STBR0SLVDMSCR);
1173 writel(0x00000000, SYS_AXI_STBR0PSLVDMSCR);
1174 writel(0x00000000, SYS_AXI_STBR0XSLVDMSCR);
1175 writel(0x00000000, SYS_AXI_STBR1SLVDMSCR);
1176 writel(0x00000000, SYS_AXI_STBR1PSLVDMSCR);
1177 writel(0x00000000, SYS_AXI_STBR1XSLVDMSCR);
1178 writel(0x00000000, SYS_AXI_STBR2SLVDMSCR);
1179 writel(0x00000000, SYS_AXI_STBR2PSLVDMSCR);
1180 writel(0x00000000, SYS_AXI_STBR2XSLVDMSCR);
1181 writel(0x00000000, SYS_AXI_STBR3SLVDMSCR);
1182 writel(0x00000000, SYS_AXI_STBR3PSLVDMSCR);
1183 writel(0x00000000, SYS_AXI_STBR3XSLVDMSCR);
1184 writel(0x00000000, SYS_AXI_STBR4SLVDMSCR);
1185 writel(0x00000000, SYS_AXI_STBR4PSLVDMSCR);
1186 writel(0x00000000, SYS_AXI_STBR4XSLVDMSCR);
1187 writel(0x00000000, SYS_AXI_ADM_DMSCR);
1188 writel(0x00000000, SYS_AXI_ADS_DMSCR);
1189
1190 /* DMS Register(RT-AXI) */
1191 writel(0x00000000, DM_AXI_DMAXICONF);
1192 writel(0x00000019, DM_AXI_DMAPBCONF);
1193 writel(0x00000000, DM_AXI_DMADMCONF);
1194 writel(0x00000000, DM_AXI_DMSDM0CONF);
1195 writel(0x00000000, DM_AXI_DMSDM1CONF);
1196 writel(0x00000004, DM_AXI_DMQSPAPSLVCONF);
1197 writel(0x00000004, DM_AXI_RAPD4SLVCONF);
1198 writel(0x00000004, DM_AXI_SAPD4SLVCONF);
1199 writel(0x00000004, DM_AXI_SAPD5SLVCONF);
1200 writel(0x00000004, DM_AXI_SAPD6SLVCONF);
1201 writel(0x00000004, DM_AXI_SAPD65DSLVCONF);
1202 writel(0x00000004, DM_AXI_SDAP0SLVCONF);
1203 writel(0x00000004, DM_AXI_MAPD2SLVCONF);
1204 writel(0x00000004, DM_AXI_MAPD3SLVCONF);
1205 writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVCONF);
1206 writel(0x00000100, DM_AXI_DMADMRQOSCONF);
1207 writel(0x0000214C, DM_AXI_DMADMRQOSCTSET0);
1208 writel(0x00000001, DM_AXI_DMADMRQOSREQCTR);
1209 writel(0x00000001, DM_AXI_DMADMRQOSQON);
1210 writel(0x00000005, DM_AXI_DMADMRQOSIN);
1211 writel(0x00000000, DM_AXI_DMADMRQOSSTAT);
1212 writel(0x00000000, DM_AXI_DMSDM0RQOSCONF);
1213 writel(0x0000214C, DM_AXI_DMSDM0RQOSCTSET0);
1214 writel(0x00000001, DM_AXI_DMSDM0RQOSREQCTR);
1215 writel(0x00000001, DM_AXI_DMSDM0RQOSQON);
1216 writel(0x00000005, DM_AXI_DMSDM0RQOSIN);
1217 writel(0x00000000, DM_AXI_DMSDM0RQOSSTAT);
1218 writel(0x00000000, DM_AXI_DMSDM1RQOSCONF);
1219 writel(0x0000214C, DM_AXI_DMSDM1RQOSCTSET0);
1220 writel(0x00000001, DM_AXI_DMSDM1RQOSREQCTR);
1221 writel(0x00000001, DM_AXI_DMSDM1RQOSQON);
1222 writel(0x00000005, DM_AXI_DMSDM1RQOSIN);
1223 writel(0x00000000, DM_AXI_DMSDM1RQOSSTAT);
1224 writel(0x00002041, DM_AXI_DMRQOSCTSET1);
1225 writel(0x00002023, DM_AXI_DMRQOSCTSET2);
1226 writel(0x0000200A, DM_AXI_DMRQOSCTSET3);
1227 writel(0x00002050, DM_AXI_DMRQOSTHRES0);
1228 writel(0x00002032, DM_AXI_DMRQOSTHRES1);
1229 writel(0x00002014, DM_AXI_DMRQOSTHRES2);
1230 writel(0x00000100, DM_AXI_DMADMWQOSCONF);
1231 writel(0x0000214C, DM_AXI_DMADMWQOSCTSET0);
1232 writel(0x00000001, DM_AXI_DMADMWQOSREQCTR);
1233 writel(0x00000001, DM_AXI_DMADMWQOSQON);
1234 writel(0x00000005, DM_AXI_DMADMWQOSIN);
1235 writel(0x00000000, DM_AXI_DMADMWQOSSTAT);
1236 writel(0x00000000, DM_AXI_DMSDM0WQOSCONF);
1237 writel(0x0000214C, DM_AXI_DMSDM0WQOSCTSET0);
1238 writel(0x00000001, DM_AXI_DMSDM0WQOSREQCTR);
1239 writel(0x00000001, DM_AXI_DMSDM0WQOSQON);
1240 writel(0x00000005, DM_AXI_DMSDM0WQOSIN);
1241 writel(0x00000000, DM_AXI_DMSDM0WQOSSTAT);
1242 writel(0x00000000, DM_AXI_DMSDM1WQOSCONF);
1243 writel(0x0000214C, DM_AXI_DMSDM1WQOSCTSET0);
1244 writel(0x00000001, DM_AXI_DMSDM1WQOSREQCTR);
1245 writel(0x00000001, DM_AXI_DMSDM1WQOSQON);
1246 writel(0x00000005, DM_AXI_DMSDM1WQOSIN);
1247 writel(0x00000000, DM_AXI_DMSDM1WQOSSTAT);
1248 writel(0x00002041, DM_AXI_DMWQOSCTSET1);
1249 writel(0x00002023, DM_AXI_DMWQOSCTSET2);
1250 writel(0x0000200A, DM_AXI_DMWQOSCTSET3);
1251 writel(0x00002050, DM_AXI_DMWQOSTHRES0);
1252 writel(0x00002032, DM_AXI_DMWQOSTHRES1);
1253 writel(0x00002014, DM_AXI_DMWQOSTHRES2);
1254 writel(0x00000000, DM_AXI_RDMDMSCR);
1255 writel(0x00000000, DM_AXI_SDM0DMSCR);
1256 writel(0x00000000, DM_AXI_SDM1DMSCR);
1257 writel(0x00000000, DM_AXI_DMQSPAPSLVDMSCR);
1258 writel(0x00000000, DM_AXI_RAPD4SLVDMSCR);
1259 writel(0x00000000, DM_AXI_SAPD4SLVDMSCR);
1260 writel(0x00000000, DM_AXI_SAPD5SLVDMSCR);
1261 writel(0x00000000, DM_AXI_SAPD6SLVDMSCR);
1262 writel(0x00000000, DM_AXI_SAPD65DSLVDMSCR);
1263 writel(0x00000000, DM_AXI_SDAP0SLVDMSCR);
1264 writel(0x00000000, DM_AXI_MAPD2SLVDMSCR);
1265 writel(0x00000000, DM_AXI_MAPD3SLVDMSCR);
1266 writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVDMSCR);
1267 writel(0x00000001, DM_AXI_DMXREGDMSENN);
1268
1269 /* DMS Register(SYS-AXI256) */
1270 writel(0x00000000, SYS_AXI256_SYXDMSCR);
1271 writel(0x00000000, SYS_AXI256_MXIDMSCR);
1272 writel(0x00000000, SYS_AXI256_X128TO256SLVDMSCR);
1273 writel(0x00000000, SYS_AXI256_X256TO128SLVDMSCR);
1274 writel(0x00000000, SYS_AXI256_SYXSLVDMSCR);
1275 writel(0x00000000, SYS_AXI256_CCXSLVDMSCR);
1276 writel(0x00000000, SYS_AXI256_S3CSLVDMSCR);
1277
1278 /* DMS Register(MXT) */
1279 writel(0x00000000, MXT_SYXDMSCR);
1280 writel(0x00000000, MXT_IMRSLVDMSCR);
1281 writel(0x00000000, MXT_VINSLVDMSCR);
1282 writel(0x00000000, MXT_VPC1SLVDMSCR);
1283 writel(0x00000000, MXT_VSPD0SLVDMSCR);
1284 writel(0x00000000, MXT_VSPD1SLVDMSCR);
1285 writel(0x00000000, MXT_MAP1SLVDMSCR);
1286 writel(0x00000000, MXT_MAP2SLVDMSCR);
1287 writel(0x00000000, MXT_MAP2BSLVDMSCR);
1288
1289 /* DMS Register(MXI) */
1290 writel(0x00000002, MXI_JPURDMSCR);
1291 writel(0x00000002, MXI_JPUWDMSCR);
1292 writel(0x00000002, MXI_VCTU0RDMSCR);
1293 writel(0x00000002, MXI_VCTU0WDMSCR);
1294 writel(0x00000002, MXI_VDCTU0RDMSCR);
1295 writel(0x00000002, MXI_VDCTU0WDMSCR);
1296 writel(0x00000002, MXI_VDCTU1RDMSCR);
1297 writel(0x00000002, MXI_VDCTU1WDMSCR);
1298 writel(0x00000002, MXI_VIN0WDMSCR);
1299 writel(0x00000002, MXI_VIN1WDMSCR);
1300 writel(0x00000002, MXI_RDRWDMSCR);
1301 writel(0x00000002, MXI_IMS01RDMSCR);
1302 writel(0x00000002, MXI_IMS01WDMSCR);
1303 writel(0x00000002, MXI_IMS23RDMSCR);
1304 writel(0x00000002, MXI_IMS23WDMSCR);
1305 writel(0x00000002, MXI_IMS45RDMSCR);
1306 writel(0x00000002, MXI_IMS45WDMSCR);
1307 writel(0x00000002, MXI_IMRRDMSCR);
1308 writel(0x00000002, MXI_IMRWDMSCR);
1309 writel(0x00000002, MXI_ROTCE4RDMSCR);
1310 writel(0x00000002, MXI_ROTCE4WDMSCR);
1311 writel(0x00000002, MXI_ROTVLC4RDMSCR);
1312 writel(0x00000002, MXI_ROTVLC4WDMSCR);
1313 writel(0x00000002, MXI_VSPD0RDMSCR);
1314 writel(0x00000002, MXI_VSPD0WDMSCR);
1315 writel(0x00000002, MXI_VSPD1RDMSCR);
1316 writel(0x00000002, MXI_VSPD1WDMSCR);
1317 writel(0x00000002, MXI_DU0RDMSCR);
1318 writel(0x00000002, MXI_DU0WDMSCR);
1319 writel(0x00000002, MXI_VSP0RDMSCR);
1320 writel(0x00000002, MXI_VSP0WDMSCR);
1321 writel(0x00000002, MXI_ROTCE0RDMSCR);
1322 writel(0x00000002, MXI_ROTCE0WDMSCR);
1323 writel(0x00000002, MXI_ROTVLC0RDMSCR);
1324 writel(0x00000002, MXI_ROTVLC0WDMSCR);
1325 writel(0x00000002, MXI_ROTCE1RDMSCR);
1326 writel(0x00000002, MXI_ROTCE1WDMSCR);
1327 writel(0x00000002, MXI_ROTVLC1RDMSCR);
1328 writel(0x00000002, MXI_ROTVLC1WDMSCR);
1329 writel(0x00000002, MXI_ROTCE2RDMSCR);
1330 writel(0x00000002, MXI_ROTCE2WDMSCR);
1331 writel(0x00000002, MXI_ROTVLC2RDMSCR);
1332 writel(0x00000002, MXI_ROTVLC2WDMSCR);
1333 writel(0x00000002, MXI_ROTCE3RDMSCR);
1334 writel(0x00000002, MXI_ROTCE3WDMSCR);
1335 writel(0x00000002, MXI_ROTVLC3RDMSCR);
1336 writel(0x00000002, MXI_ROTVLC3WDMSCR);
1337
1338 /* DMS Register(CCI-AXI) */
1339 writel(0x00000000, CCI_AXI_MMUS0DMSCR);
1340 writel(0x00000000, CCI_AXI_SYX2DMSCR);
1341 writel(0x00000000, CCI_AXI_MMURDMSCR);
1342 writel(0x00000000, CCI_AXI_MMUDSDMSCR);
1343 writel(0x00000000, CCI_AXI_MMUMDMSCR);
1344 writel(0x00000000, CCI_AXI_MXIDMSCR);
1345 writel(0x00000000, CCI_AXI_MMUS1DMSCR);
1346 writel(0x00000000, CCI_AXI_MMUMPDMSCR);
1347 writel(0x00000000, CCI_AXI_DVMDMSCR);
1348 writel(0x00000000, CCI_AXI_CCISLVDMSCR);
1349
1350 /* CC-AXI Function Register */
1351 writel(0x00000011, CCI_AXI_IPMMUIDVMCR);
1352 writel(0x00000011, CCI_AXI_IPMMURDVMCR);
1353 writel(0x00000011, CCI_AXI_IPMMUS0DVMCR);
1354 writel(0x00000011, CCI_AXI_IPMMUS1DVMCR);
1355 writel(0x00000011, CCI_AXI_IPMMUMPDVMCR);
1356 writel(0x00000011, CCI_AXI_IPMMUDSDVMCR);
1357 writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
1358
1359}
Marek Vasutd26aa8c2024-02-27 17:05:53 +0100[diff] [blame]1360#else /* CONFIG_RENESAS_EXTRAM_BOOT */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]1361void qos_init(void)
1362{
1363}
Marek Vasutd26aa8c2024-02-27 17:05:53 +0100[diff] [blame]1364#endif /* CONFIG_RENESAS_EXTRAM_BOOT */