Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 4 | * Copyright 2020 Hitachi Power Grids. All rights reserved. |
| 5 | */ |
| 6 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 7 | #include <config.h> |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 8 | #include <fsl_ddr_sdram.h> |
| 9 | #include <fsl_ddr_dimm_params.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/global_data.h> |
| 13 | #include <asm/arch/ls102xa_soc.h> |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | void fsl_ddr_board_options(memctl_options_t *popts, |
| 18 | dimm_params_t *pdimm, |
| 19 | unsigned int ctrl_num) |
| 20 | { |
| 21 | if (ctrl_num > 1) { |
| 22 | printf("Not supported controller number %d\n", ctrl_num); |
| 23 | return; |
| 24 | } |
| 25 | |
| 26 | // 1/2 DRAM cycle (should be increased in case of ADDR/CMD heavily loaded than the clock) |
| 27 | popts->clk_adjust = 0x4; |
| 28 | popts->write_data_delay = 0x4; |
| 29 | // wr leveling start value for lane 0 |
| 30 | popts->wrlvl_start = 0x5; |
| 31 | // wr leveling start values for lanes 1-3 (lane 4 not there) |
| 32 | popts->wrlvl_ctl_2 = 0x05050500; |
| 33 | // 32-bit DRAM, no need to set start values for lanes we do not have (5-8) |
| 34 | popts->wrlvl_ctl_3 = 0x0; |
| 35 | popts->cpo_override = 0x1f; |
| 36 | |
| 37 | /* force DDR bus width to 32 bits */ |
| 38 | popts->data_bus_width = 1; |
| 39 | popts->otf_burst_chop_en = 0; |
| 40 | popts->burst_length = DDR_BL8; |
| 41 | |
| 42 | /* |
| 43 | * Factors to consider for half-strength driver enable: |
| 44 | * - number of DIMMs installed |
| 45 | */ |
| 46 | popts->half_strength_driver_enable = 1; |
| 47 | /* |
| 48 | * Write leveling override |
| 49 | */ |
| 50 | popts->wrlvl_override = 1; |
| 51 | popts->wrlvl_sample = 0xf; |
| 52 | |
| 53 | /* |
| 54 | * Rtt and Rtt_WR override |
| 55 | */ |
| 56 | popts->rtt_override = 0; |
| 57 | |
| 58 | /* Enable ZQ calibration */ |
| 59 | popts->zq_en = 1; |
| 60 | |
| 61 | popts->cswl_override = DDR_CSWL_CS0; |
| 62 | |
| 63 | /* optimize cpo for erratum A-009942 */ |
| 64 | popts->cpo_sample = 0x58; |
| 65 | |
| 66 | /* DHC_EN =1, ODT = 75 Ohm */ |
| 67 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
| 68 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
| 69 | } |
| 70 | |
| 71 | int fsl_initdram(void) |
| 72 | { |
| 73 | phys_size_t dram_size; |
| 74 | |
| 75 | puts("Initializing DDR....using SPD\n"); |
| 76 | dram_size = fsl_ddr_sdram(); |
| 77 | |
| 78 | erratum_a008850_post(); |
| 79 | |
| 80 | gd->ram_size = dram_size; |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | int dram_init_banksize(void) |
| 86 | { |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 87 | gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 88 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 89 | |
| 90 | return 0; |
| 91 | } |