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git01.mediatek.com / filogic / uboot / f912a72595fa4e3bf55f2788183f9481b7165ac7 / . / include / vesa.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: BSD-2-Clause */
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]2/******************************************************************************
3 * Copyright (c) 2004, 2008 IBM Corporation
4 * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
5 * All rights reserved.
6 *
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]7 * Contributors:
8 * IBM Corporation - initial implementation
9 *****************************************************************************/
Simon Glassec86bc62022-07-30 15:52:04 -0600[diff] [blame]10#ifndef _VESA_H
11#define _VESA_H
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]12
13/* these structs are for input from and output to OF */
Simon Glass5b925202022-07-30 15:52:05 -0600[diff] [blame]14struct __packed vesa_screen_info {
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]15 u8 display_type; /* 0=NONE, 1= analog, 2=digital */
16 u16 screen_width;
17 u16 screen_height;
18 /* bytes per line in framebuffer, may be more than screen_width */
19 u16 screen_linebytes;
20 u8 color_depth; /* color depth in bits per pixel */
21 u32 framebuffer_address;
22 u8 edid_block_zero[128];
23};
24
Simon Glass5b925202022-07-30 15:52:05 -0600[diff] [blame]25struct __packed vesa_screen_info_input {
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]26 u8 signature[4];
27 u16 size_reserved;
28 u8 monitor_number;
29 u16 max_screen_width;
30 u8 color_depth;
31};
32
Simon Glass5b925202022-07-30 15:52:05 -0600[diff] [blame]33/*
34 * These structs only store the required subset of fields in Vesa BIOS
35 * Extensions
36 */
37struct __packed vesa_bios_ext_info {
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]38 char signature[4];
39 u16 version;
Simon Glassc55b1c62014-12-29 19:32:26 -0700[diff] [blame]40 u32 oem_string_ptr;
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]41 u32 capabilities;
Simon Glassc55b1c62014-12-29 19:32:26 -0700[diff] [blame]42 u32 modes_ptr;
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]43 u16 total_memory;
Simon Glassc55b1c62014-12-29 19:32:26 -0700[diff] [blame]44 u16 oem_version;
45 u32 vendor_name_ptr;
46 u32 product_name_ptr;
47 u32 product_rev_ptr;
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]48};
49
50struct __packed vesa_mode_info {
51 u16 mode_attributes; /* 00 */
52 u8 win_a_attributes; /* 02 */
53 u8 win_b_attributes; /* 03 */
54 u16 win_granularity; /* 04 */
55 u16 win_size; /* 06 */
56 u16 win_a_segment; /* 08 */
57 u16 win_b_segment; /* 0a */
58 u32 win_func_ptr; /* 0c */
59 u16 bytes_per_scanline; /* 10 */
60 u16 x_resolution; /* 12 */
61 u16 y_resolution; /* 14 */
62 u8 x_charsize; /* 16 */
63 u8 y_charsize; /* 17 */
64 u8 number_of_planes; /* 18 */
65 u8 bits_per_pixel; /* 19 */
66 u8 number_of_banks; /* 20 */
67 u8 memory_model; /* 21 */
68 u8 bank_size; /* 22 */
69 u8 number_of_image_pages; /* 23 */
70 u8 reserved_page;
71 u8 red_mask_size;
72 u8 red_mask_pos;
73 u8 green_mask_size;
74 u8 green_mask_pos;
75 u8 blue_mask_size;
76 u8 blue_mask_pos;
77 u8 reserved_mask_size;
78 u8 reserved_mask_pos;
79 u8 direct_color_mode_info;
80 u32 phys_base_ptr;
81 u32 offscreen_mem_offset;
82 u16 offscreen_mem_size;
83 u8 reserved[206];
84};
85
Simon Glass5b925202022-07-30 15:52:05 -0600[diff] [blame]86struct vesa_state {
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]87 u16 video_mode;
88 bool valid;
89 union {
90 struct vesa_mode_info vesa;
91 u8 mode_info_block[256];
92 };
93};
94
Simon Glass5b925202022-07-30 15:52:05 -0600[diff] [blame]95struct vesa_ddc_info {
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]96 u8 port_number; /* i.e. monitor number */
97 u8 edid_transfer_time;
98 u8 ddc_level;
99 u8 edid_block_zero[128];
100};
101
102#define VESA_GET_INFO 0x4f00
103#define VESA_GET_MODE_INFO 0x4f01
104#define VESA_SET_MODE 0x4f02
Simon Glassc55b1c62014-12-29 19:32:26 -0700[diff] [blame]105#define VESA_GET_CUR_MODE 0x4f03
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]106
Simon Glass5b925202022-07-30 15:52:05 -0600[diff] [blame]107extern struct vesa_state mode_info;
Bin Mengc8990bd2015-08-13 00:29:16 -0700[diff] [blame]108
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600[diff] [blame]109struct video_priv;
Simon Glassb75b15b2020-12-03 16:55:23 -0700[diff] [blame]110struct video_uc_plat;
Simon Glass5b925202022-07-30 15:52:05 -0600[diff] [blame]111int vesa_setup_video_priv(struct vesa_mode_info *vesa,
112 struct video_priv *uc_priv,
113 struct video_uc_plat *plat);
114int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void));
Simon Glasse518f4e2014-11-14 20:56:31 -0700[diff] [blame]115
116#endif