Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Gateworks Corporation |
| 4 | * Author: Tim Harvey <tharvey@gateworks.com> |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __IMX6_SPL_CONFIG_H |
| 7 | #define __IMX6_SPL_CONFIG_H |
| 8 | |
| 9 | #ifdef CONFIG_SPL |
Robert Hancock | 9c5970c | 2019-08-08 12:14:39 -0600 | [diff] [blame] | 10 | |
| 11 | #ifdef CONFIG_MX6_OCRAM_256KB |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 12 | /* |
Robert Hancock | 9c5970c | 2019-08-08 12:14:39 -0600 | [diff] [blame] | 13 | * see Figure 8.4.1 in IMX6DQ Reference manuals: |
| 14 | * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF |
| 15 | * - BOOT ROM stack is at 0x0093FFB8 |
| 16 | * - if icache/dcache is enabled (eFuse/strapping controlled) then the |
| 17 | * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to |
| 18 | * fit between 0x00907000 and 0x00938000. |
| 19 | * - Additionally the BOOT ROM loads what they consider the firmware image |
| 20 | * which consists of a 4K header in front of us that contains the IVT, DCD |
| 21 | * and some padding thus 'our' max size is really 0x00908000 - 0x00938000 |
| 22 | * or 192KB |
| 23 | */ |
Robert Hancock | 9c5970c | 2019-08-08 12:14:39 -0600 | [diff] [blame] | 24 | #define CONFIG_SPL_STACK 0x0093FFB8 |
| 25 | /* |
| 26 | * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the |
| 27 | * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a |
| 28 | * boot media (given that boot media specific offset is configured properly). |
| 29 | */ |
Robert Hancock | 9c5970c | 2019-08-08 12:14:39 -0600 | [diff] [blame] | 30 | #else |
| 31 | /* |
| 32 | * see Figure 8-3 in IMX6SDL Reference manuals: |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 33 | * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 34 | * - BOOT ROM stack is at 0x0091FFB8 |
| 35 | * - if icache/dcache is enabled (eFuse/strapping controlled) then the |
| 36 | * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to |
| 37 | * fit between 0x00907000 and 0x00918000. |
| 38 | * - Additionally the BOOT ROM loads what they consider the firmware image |
| 39 | * which consists of a 4K header in front of us that contains the IVT, DCD |
| 40 | * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 |
| 41 | * or 64KB |
| 42 | */ |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 43 | #define CONFIG_SPL_STACK 0x0091FFB8 |
Stefan Agner | 003b63b | 2016-11-15 10:38:23 -0800 | [diff] [blame] | 44 | /* |
| 45 | * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the |
| 46 | * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a |
| 47 | * boot media (given that boot media specific offset is configured properly). |
| 48 | */ |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 49 | |
Robert Hancock | 9c5970c | 2019-08-08 12:14:39 -0600 | [diff] [blame] | 50 | #endif |
| 51 | |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 52 | /* MMC support */ |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 53 | #if defined(CONFIG_SPL_MMC) |
Semen Protsenko | d776ecf | 2016-11-16 19:19:06 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 55 | #endif |
| 56 | |
| 57 | /* SATA support */ |
Simon Glass | 081a45a | 2021-08-08 12:20:17 -0600 | [diff] [blame] | 58 | #if defined(CONFIG_SPL_SATA) |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 59 | #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 |
| 60 | #endif |
| 61 | |
Fabio Estevam | 1b691df | 2018-01-03 12:33:05 -0200 | [diff] [blame] | 62 | #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ |
| 63 | defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) |
Peng Fan | 327083c | 2014-12-30 17:24:02 +0800 | [diff] [blame] | 64 | #define CONFIG_SPL_BSS_START_ADDR 0x88200000 |
Peng Fan | 327083c | 2014-12-30 17:24:02 +0800 | [diff] [blame] | 65 | #define CONFIG_SYS_SPL_MALLOC_START 0x88300000 |
Marek Vasut | 75801c1 | 2015-11-20 21:43:24 +0100 | [diff] [blame] | 66 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ |
Peng Fan | 327083c | 2014-12-30 17:24:02 +0800 | [diff] [blame] | 67 | #else |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 68 | #define CONFIG_SPL_BSS_START_ADDR 0x18200000 |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 69 | #define CONFIG_SYS_SPL_MALLOC_START 0x18300000 |
Marek Vasut | 75801c1 | 2015-11-20 21:43:24 +0100 | [diff] [blame] | 70 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 71 | #endif |
Peng Fan | 327083c | 2014-12-30 17:24:02 +0800 | [diff] [blame] | 72 | #endif |
Tim Harvey | 7412d9d | 2014-06-02 16:13:19 -0700 | [diff] [blame] | 73 | |
| 74 | #endif |