blob: 08eb0dbbf954b51163a0f62470a1f590a38ca16f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Dirk Eibachfb605942017-02-22 16:07:23 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
Dirk Eibachfb605942017-02-22 16:07:23 +01005 */
6
7#ifndef _CONFIG_CONTROLCENTERDC_H
8#define _CONFIG_CONTROLCENTERDC_H
9
10/*
Dirk Eibachfb605942017-02-22 16:07:23 +010011 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
12 * for DDR ECC byte filling in the SPL before loading the main
13 * U-Boot into it.
14 */
Dirk Eibachfb605942017-02-22 16:07:23 +010015
Dirk Eibachfb605942017-02-22 16:07:23 +010016/* Environment in SPI NOR flash */
Dirk Eibachfb605942017-02-22 16:07:23 +010017
Dirk Eibachfb605942017-02-22 16:07:23 +010018#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
19
20/* PCIe support */
21#ifndef CONFIG_SPL_BUILD
Dirk Eibachfb605942017-02-22 16:07:23 +010022#define CONFIG_PCI_SCAN_SHOW
23#endif
24
Dirk Eibachfb605942017-02-22 16:07:23 +010025/* SPL */
26/*
27 * Select the boot device here
28 *
29 * Currently supported are:
30 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
31 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
32 */
33#define SPL_BOOT_SPI_NOR_FLASH 1
34#define SPL_BOOT_SDIO_MMC_CARD 2
35#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
36
37/* Defines for SPL */
Dirk Eibachfb605942017-02-22 16:07:23 +010038#define CONFIG_SPL_SIZE (160 << 10)
39
Dirk Eibachfb605942017-02-22 16:07:23 +010040#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
Dirk Eibachfb605942017-02-22 16:07:23 +010041
Dirk Eibachfb605942017-02-22 16:07:23 +010042#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
43#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
44
Dirk Eibachfb605942017-02-22 16:07:23 +010045#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
46/* SPL related MMC defines */
Dirk Eibachfb605942017-02-22 16:07:23 +010047#ifdef CONFIG_SPL_BUILD
48#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
49#endif
50#endif
51
52/*
53 * Environment Configuration
54 */
Dirk Eibachfb605942017-02-22 16:07:23 +010055
Mario Six790d8442018-03-28 14:38:20 +020056#define CONFIG_HOSTNAME "ccdc"
Dirk Eibachfb605942017-02-22 16:07:23 +010057#define CONFIG_ROOTPATH "/opt/nfsroot"
Dirk Eibachfb605942017-02-22 16:07:23 +010058
Dirk Eibachfb605942017-02-22 16:07:23 +010059#define CONFIG_EXTRA_ENV_SETTINGS \
60 "netdev=eth1\0" \
61 "consoledev=ttyS1\0" \
62 "u-boot=u-boot.bin\0" \
63 "bootfile_addr=1000000\0" \
64 "keyprogram_addr=3000000\0" \
65 "keyprogram_file=keyprogram.img\0" \
66 "fdtfile=controlcenterdc.dtb\0" \
67 "load=tftpboot ${loadaddr} ${u-boot}\0" \
68 "mmcdev=0:2\0" \
69 "update=sf probe 1:0;" \
70 " sf erase 0 +${filesize};" \
71 " sf write ${fileaddr} 0 ${filesize}\0" \
72 "upd=run load update\0" \
73 "fdt_high=0x10000000\0" \
74 "initrd_high=0x10000000\0" \
75 "loadkeyprogram=tpm flush_keys;" \
76 " mmc rescan;" \
77 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
78 " source ${keyprogram_addr}:script@1\0" \
79 "gpio1=gpio@22_25\0" \
80 "gpio2=A29\0" \
81 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \
82 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \
83 "bootfail=for i in ${blinkseq}; do" \
84 " if test $i -eq 0; then" \
85 " gpio clear ${gpio1}; gpio set ${gpio2};" \
86 " elif test $i -eq 1; then" \
87 " gpio clear ${gpio1}; gpio clear ${gpio2};" \
88 " elif test $i -eq 2; then" \
89 " gpio set ${gpio1}; gpio set ${gpio2};" \
90 " else;" \
91 " gpio clear ${gpio1}; gpio set ${gpio2};" \
92 " fi; sleep 0.12; done\0"
93
Dirk Eibachfb605942017-02-22 16:07:23 +010094/*
95 * mv-common.h should be defined after CMD configs since it used them
96 * to enable certain macros
97 */
98#include "mv-common.h"
99
100#endif /* _CONFIG_CONTROLCENTERDC_H */