Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / f8d0ae132a53251d75328e3502d6c11ed81a9234 / . / include / configs / tegra30-common.h
blob: 0b69776315c60151f7a635f771bbee6c1ceec647 [file] [log] [blame]
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]1/*
2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]6 */
7
8#ifndef _TEGRA30_COMMON_H_
9#define _TEGRA30_COMMON_H_
10#include "tegra-common.h"
11
12/*
13 * NS16550 Configuration
14 */
15#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
16
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]17/*
18 * Miscellaneous configurable options
19 */
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]20#define CONFIG_STACKBASE 0x82800000 /* 40MB */
21
22/*-----------------------------------------------------------------------
23 * Physical Memory Map
24 */
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]25
26/*
27 * Memory layout for where various images get loaded by boot scripts:
28 *
29 * scriptaddr can be pretty much anywhere that doesn't conflict with something
30 * else. Put it above BOOTMAPSZ to eliminate conflicts.
31 *
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]32 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
33 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
34 *
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]35 * kernel_addr_r must be within the first 128M of RAM in order for the
36 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
37 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
38 * should not overlap that area, or the kernel will have to copy itself
39 * somewhere else before decompression. Similarly, the address of any other
40 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
41 * this up to 16M allows for a sizable kernel to be decompressed below the
42 * compressed load address.
43 *
44 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
45 * the compressed kernel to be up to 16M too.
46 *
47 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
48 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
49 */
Stephen Warrenf61f1292015-04-01 15:40:53 -0600[diff] [blame]50#define CONFIG_LOADADDR 0x81000000
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]51#define MEM_LAYOUT_ENV_SETTINGS \
52 "scriptaddr=0x90000000\0" \
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]53 "pxefile_addr_r=0x90100000\0" \
Stephen Warrenf61f1292015-04-01 15:40:53 -0600[diff] [blame]54 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]55 "fdt_addr_r=0x82000000\0" \
56 "ramdisk_addr_r=0x82100000\0"
57
58/* Defines for SPL */
59#define CONFIG_SPL_TEXT_BASE 0x80108000
60#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
61#define CONFIG_SPL_STACK 0x800ffffc
62
Jim Lin68c0c02c2013-06-21 19:05:48 +0800[diff] [blame]63/* For USB EHCI controller */
64#define CONFIG_EHCI_IS_TDI
Jim Lincbb4c5e2013-11-06 14:03:44 +0800[diff] [blame]65#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
Jim Lin68c0c02c2013-06-21 19:05:48 +0800[diff] [blame]66
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]67#endif /* _TEGRA30_COMMON_H_ */